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2011 (English)In: Proceedings - 6th International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2011, IEEE conference proceedings, 2011, p. 127-132Conference paper, Published paper (Refereed)
Abstract [en]
In this paper we have explored different possibilities for partitioning the tasks between hardware, software and locality for the implementation of the vision sensor node, used in wireless vision sensor network. Wireless vision sensor network is an emerging field which combines image sensor, on board computation and communication links. Compared to the traditional wireless sensor networks which operate on one dimensional data, wireless vision sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. The research focus within the field of wireless vision sensor networks have been on two different assumptions involving either sending raw data to the central base station without local processing or conducting all processing locally at the sensor node and transmitting only the final results. Our research work focus on determining an optimal point of hardware/software partitioning as well as partitioning between local and central processing, based on minimum energy consumption for vision processing operation. The lifetime of the vision sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of FPGA and micro controller for the implementation of the vision sensor node. Our results show that sending compressed images after pixel based tasks will result in a longer battery life time with reasonable hardware cost for the vision sensor node. © 2011 IEEE.
Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keywords
Hardware/Software Partioning, Image Processing, Reconfigurable Architecture, Vision Sensor Node, Wireless Vision Sensor Networks, Battery life time, Communication bandwidth, Compressed images, Embedded platforms, Energy requirements, Hardware cost, Hardware/software partitioning, Local processing, Minimum energy, Optimal points, Partioning, Processing power, Vision processing, Vision sensors, Wireless cameras, Work Focus, Computer hardware, Electrical engineering, Energy utilization, Engineering research, Field programmable gate arrays (FPGA), Parallel architectures, Sensors, Telecommunication equipment, Telecommunication systems, Wireless networks, Sensor nodes
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-14195 (URN)10.1109/PARELEC.2011.21 (DOI)2-s2.0-79958725347 (Scopus ID)STC (Local ID)9780769543970 (ISBN)STC (Archive number)STC (OAI)
Conference
6th International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2011; Luton; 4 April 2011 through 5 April 2011; Category number E4397; Code 85105
2011-07-192011-07-192025-09-25Bibliographically approved