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Real-time Component Labelling and Feature Extraction on FPGA
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.ORCID iD: 0000-0002-3429-273X
2009 (English)In: 2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009, IEEE conference proceedings, 2009, p. 5206100-Conference paper, Published paper (Refereed)
Abstract [en]

We present in this work an image component labeller- and feature extraction module that can operate in real-time. This labeller is suitable for smart cameras and Field Programmable Gate Arrays (FPGA). We show in our work how complex gray value features of image components can be calculated in parallel with label assignment without first resolving complex chains of merged labels. The labeller and a simple counter of number of image components are implemented on a Xilinx Virtex II Pro. We report device usage, maximum frequency and power dissipation.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2009. p. 5206100-
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-10752DOI: 10.1109/ISSCS.2009.5206100ISI: 000275854200054Scopus ID: 2-s2.0-70449496521ISBN: 978-142443786-3 (print)OAI: oai:DiVA.org:miun-10752DiVA, id: diva2:282501
Conference
2009 International Symposium on Signals, Circuits and Systems, ISSCS 2009; Iasi; 9 July 2009 through 10 July 2009
Available from: 2009-12-21 Created: 2009-12-21 Last updated: 2025-09-25Bibliographically approved

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Thörnberg, BennyLawal, Najeem

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CiteExportLink to record
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Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
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Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf