Mid Sweden University

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.

The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.