Mid Sweden University

Several system specification languages are emerging from C and C++. This development is driven by the large competence that exists for these languages. The programming language itself lacks many of the necessary constructs one requires from a specification language. Therefore, specification languages based on C/C++ are often a superset of the programming language. Where all the necessary constructs for system specification is added to the language. This paper evaluates and compares SystemC and Ocapi, which both are specification methods based on C++. The analysis is done as a case study with focus on the modelling and simulation effectiveness for video systems. The system we have selected is a spatio-temporal video filter. This video filter is characterised by high computational complexity, by high requirements on memory size and memory bandwidth.

Most operations invoked in video processing systems are neighborhood oriented. For a video system designer, this limited spatio-temporal collection of pixels represents a natural abstraction. In this paper, we present a basic set of object-oriented design entities. Entities, which can be combined to capture an interface and memory model at a conceptual level, with the neighborhood as an abstraction. These design entities, called IMEM, are implemented as an extension to SystemC. IMEM supports conceptual modeling that excludes implementation details and has explicit data dependency built-in to the model. This makes IMEM a very efficient starting point for design-space exploration and system synthesis. We propose two workflows. The first is a system development workflow, where IMEM represents the starting point of a gradual refinement process, supported by an automated design space exploration step. The second workflow, based on direct mapping of the interface and memory model is presented as being suitable for rapid prototyping. A spatio-temporal noise-reduction filter is selected as a test-vehicle in order to demonstrate the feasibility of IMEM.

We present a source-code generator for real-time video processing systems that automatically optimise the cache and scheduler performance for selected target architectures. Code can be directly generated from a modelled neighbourhood without any additional data dependency analysis. Experimental results show that almost all data cache misses are removed and we can see a reduction of the execution time in the order of 25 percent compared to non-tuned code. The source-code generator is a part of an automated and target independent development trajectory and motivated by improved designer productivity.

We present a tool and a methodology for estimating the memory storage requirement for synchronous real-time video processing systems. Typically, a designer will use the feedback information from this estimation to select the most optimal execution order for software processors or space to time mapping for hardware. We propose to start from a conceptual interface and memory model that captures memory usage and data transfers. This high-level modeling is provided as an extension library of SystemC called IMEM. A common polyhedral iteration space is generated from the model, where polytopes are placed using a new placement algorithm based on simple heuristics. This algorithm will ensure maximum freedom of selecting executing order as all negative dependencies are removed to the length of zero. A demonstration is given regarding how the polytopes and dependency vectors can then be used as input to a memory storage estimation tool called STOREQ.

This paper presents a comparison of local and global memory allocation for implementation of real-time video processing systems on FPGAs. The paper compares new methods to perform memory allocation using single and dual port block RAMs to memory allocation methods found in the literature. This investigation shows that the use of global allocation can reduce the memory size by up to 75 % for the two presented video processing systems.

We present an optimization model for the allocation of shift registers to dual ported FPGA memory blocks. Shift registers are used in real-time video processing for the storage of data flow dependencies. The model is formalized into a mixed integer linear program that can be executed using a general solver. Allocation results from realistic video systems verify the correctness of the model. This model serves as a formal specification and setup for the development of an efficient allocation heuristic.

The great variety of pixel dynamics of real-time video processing systems, ranging from color, grayscale or binary pixels, means that a careful design and specification of bit-widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. A real-life surveillance system is introduced, as a demonstration application showing how the optimal allocation of shift registers for the storage of intermediate results is sensitive to bit-widths. From this we conclude, that careful memory hierarchy design where bit-widths are considered can reduce the total on-chip memory storage requirement by 61 percent compared to a non-optimal design.

The great variety of pixel dynamics of real-time video processing systems, ranging from color, grayscale or binary pixels, means that a careful design and specification of bit-widths is required. It is obvious that the bit-width specification will affect the total memory storage requirement. However, what is not so obvious is that the bit-width specification will also affect the design of the memory hierarchy, an impact similar for both hardware and software implementations. We have developed an Integer Non Linear Program (INLP) formulation for the optimization of the memory hierarchy of real-time video processing systems. An active surveillance video camera is introduced as a test case. We demonstrate how the optimization model can reduce the on-chip memory storage by 61 percent compared to a non optimal memory hierarchy.