Mittuniversitetet

Replacing planar circuits with vertically integrated ones allows to increment circuit functionalities on a given silicon area, while avoiding some of the problems associated with aggressively scaled technology nodes. This is particularly true for applications likely to subject circuits to high doses of ionizing radiation (such of x-ray detectors to be used in synchrotron rings and Free Electron Lasers), since the degradation mechanisms of some of the innovative materials to be used in most recent nodes have not been fully characterized yet. In this paper, an evolution is presented for the readout ASIC of a pixelated x-ray detector to be used for such applications. The readout circuit is distributed in a stack of two vertically interconnected tiers, thus doubling the circuitry resident in each pixel without increasing the pixel pitch (and thus compromising spatial resolution of the detector). A first prototype has been designed and manufactured, using a commercial 130 nm CMOS technology. Design issues are discussed, along with preliminary characterization results. © 2014 IEEE.