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  • 51.
    Khursheed, Khursheed
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Ahmad, Naeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Efficient Data Reduction Techniques for Remote Applications of a Wireless Visual Sensor Network2013In: International Journal of Advanced Robotic Systems, ISSN 1729-8806, E-ISSN 1729-8814, Vol. 10, p. Art. no. 240-Article in journal (Refereed)
    Abstract [en]

    A Wireless Visual Sensor Network (WVSN) is formed by deploying many Visual Sensor Nodes (VSNs) in the field. After acquiring an image of the area of interest, the VSN performs local processing on it and transmits the result using an embedded wireless transceiver. Wireless data transmission consumes a great deal of energy, where energy consumption is mainly dependent on the amount of information being transmitted. The image captured by the VSN contains a huge amount of data. For certain applications, segmentation can be performed on the captured images. The amount of information in the segmented images can be reduced by applying efficient bi-level image compression methods. In this way, the communication energy consumption of each of the VSNs can be reduced. However, the data reduction capability of bi-level image compression standards is fixed and is limited by the used compression algorithm. For applications attributing few changes in adjacent frames, change coding can be applied for further data reduction. Detecting and compressing only the Regions of Interest (ROIs) in the change frame is another possibility for further data reduction. In a communication system, where both the sender and the receiver know the employed compression standard, there is a possibility for further data reduction by not including the header information in the compressed bit stream of the sender. This paper summarizes different information reduction techniques such as image coding, change coding and ROI coding. The main contribution is the investigation of the combined effect of all these coding methods and their application to a few representative real life applications. This paper is intended to be a resource for researchers interested in techniques for information reduction in energy constrained embedded applications.

  • 52.
    Khursheed, Khursheed
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ahmad, Naeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Selection of bi-level image compression method for reduction of communication energy in wireless visual sensor networks2012In: SPIE: Proc. SPIE 8437, 84370M (2012), 2012Conference paper (Refereed)
    Abstract [en]

    Wireless Visual Sensor Network (WVSN) is an emerging field which combines image sensor, on board computation unit, communication component and energy source. Compared to the traditional wireless sensor network, which operates on one dimensional data, such as temperature, pressure values etc., WVSN operates on two dimensional data (images) which requires higher processing power and communication bandwidth. Normally, WVSNs are deployed in areas where installation of wired solutions is not feasible. The energy budget in these networks is limited to the batteries, because of the wireless nature of the application. Due to the limited availability of energy, the processing at Visual Sensor Nodes (VSN) and communication from VSN to server should consume as low energy as possible. Transmission of raw images wirelessly consumes a lot of energy and requires higher communication bandwidth. Data compression methods reduce data efficiently and hence will be effective in reducing communication cost in WVSN. In this paper, we have compared the compression efficiency and complexity of six well known bi-level image compression methods. The focus is to determine the compression algorithms which can efficiently compress bi-level images and their computational complexity is suitable for computational platform used in WVSNs. These results can be used as a road map for selection of compression methods for different sets of constraints in WVSN.

  • 53.
    Khursheed, Khursheed
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Malik, Abdul Waheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Exploration of tasks partitioning between hardware software and locality for a wireless camera based vision sensor node2011In: Proceedings - 6th International Symposium on Parallel Computing in Electrical Engineering, PARELEC 2011, IEEE conference proceedings, 2011, p. 127-132Conference paper (Refereed)
    Abstract [en]

    In this paper we have explored different possibilities for partitioning the tasks between hardware, software and locality for the implementation of the vision sensor node, used in wireless vision sensor network. Wireless vision sensor network is an emerging field which combines image sensor, on board computation and communication links. Compared to the traditional wireless sensor networks which operate on one dimensional data, wireless vision sensor networks operate on two dimensional data which requires higher processing power and communication bandwidth. The research focus within the field of wireless vision sensor networks have been on two different assumptions involving either sending raw data to the central base station without local processing or conducting all processing locally at the sensor node and transmitting only the final results. Our research work focus on determining an optimal point of hardware/software partitioning as well as partitioning between local and central processing, based on minimum energy consumption for vision processing operation. The lifetime of the vision sensor node is predicted by evaluating the energy requirement of the embedded platform with a combination of FPGA and micro controller for the implementation of the vision sensor node. Our results show that sending compressed images after pixel based tasks will result in a longer battery life time with reasonable hardware cost for the vision sensor node. © 2011 IEEE.

  • 54.
    Khursheed, Khursheed
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Exploration of Local and Central Processing for a Wireless Camera Based Sensor Node2010In: International Conference on Signals and Electronic Systems, ICSES'10 - Conference Proceeding 2010, Article number 5595231, IEEE conference proceedings, 2010, p. 147-150Conference paper (Refereed)
    Abstract [en]

    Wireless vision sensor network is an emerging field which combines image sensor, on board computation and communication links. Compared to the traditional wireless sensor networks which operate on one dimensional data, wireless vision sensor networks operate on two dimensional data which requires both higher processing power and communication bandwidth. The research focus within the field of wireless vision sensor network has been based on two different assumptions involving either sending data to the central base station without local processing or conducting all processing locally at the sensor node and transmitting only the final results. In this paper we focus on determining an optimal point for intelligence partitioning between the sensor node and the central base station and by exploring compression methods. The lifetime of the visual sensor node is predicted by evaluating the energy consumption for different levels of intelligence partitioning at the sensor node. Our results show that sending compressed images after segmentation will result in a longer life for the sensor node.

  • 55.
    Krug, Silvia
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Bader, Sebastian
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Suitability of Communication Technologies for Harvester-Powered IoT-Nodes2019In: IEEE International Workshop on Factory Communication Systems - Proceedings, WFCS, Institute of Electrical and Electronics Engineers (IEEE), 2019, article id 8758042Conference paper (Refereed)
    Abstract [en]

    The Internet of Things introduces Internet connectivity to things and objects in the physical world and thus enables them to communicate with other nodes via the Internet directly. This enables new applications that for example allow seamless process monitoring and control in industrial environments. One core requirement is that the nodes involved in the network have a long system lifetime, despite limited access to the power grid and potentially difficult propagation conditions. Energy harvesting can provide the required energy for this long lifetime if the node is able to send the data based on the available energy budget. In this paper, we therefore analyze and evaluate which common IoT communication technologies are suitable for nodes powered by energy harvesters. The comparison includes three different constraints from different energy sources and harvesting technologies besides several communication technologies. Besides identifying possible technologies in general, we evaluate the impact of duty-cycling and different data sizes. The results in this paper give a road map for combining energy harvesting technology with IoT communication technology to design industrial sensor nodes. 

  • 56.
    Krug, Silvia
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    IoT Communication Introduced Limitations for High Sampling Rate Applications2018In: GI/ITG KuVS Fachgespräch Sensornetze 13. & 14. September 2018, Braunschweig : Technical Report, 2018Conference paper (Refereed)
    Abstract [en]

    Networking solutions for the Internet of Things aretypically designed for applications that require low data rates andfeature rare transmission events. The initial assumption leads to asystem design towards minimal data transfers and packet sizes.However, this can become a challenge, if applications requiredifferent traffic patterns or cooperative interaction betweendevices. Applications requiring a high sampling rate to capturethe desired phenomenon produce larger amounts of data thatneed to be transported. In this paper, we present a studyhighlighting some of the challenging aspects for such applicationsand how the choice of communication technology can limit bothapplication behavior and network structure.

  • 57.
    Krug, Silvia
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Modeling and Comparison of Delay and Energy Cost of IoT Data Transfers2019In: IEEE Access, E-ISSN 2169-3536, Vol. 7, p. 58654-58675Article in journal (Refereed)
    Abstract [en]

    Communication is often considered as the most costly component of a wireless sensor node. As a result, a variety of technologies and protocols aim to reduce the energy consumption for the communication especially in the Internet of Things context. In order to select the best suitable technology for a given use case, a tool that allows the comparison of these options is needed. The goal of this paper is to introduce a new modular modeling framework that enables a comparison of various technologies based on analytical calculations. We chose to model the cost for a single data transfer of arbitrary application data amounts in order to provide flexibility regarding the data amount and traffic patterns. The modeling approach covers the stack traversal of application data and thus in comparison to other approaches includes the required protocol overhead directly. By applying our models to different data amounts, we are able to show tradeoffs between various technologies and enable comparisons for different scenarios. In addition, our results reveal the impact of design decisions that can help to identify future development challenges.

  • 58.
    Krug, Silvia
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Shallari, Irida
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    A Case Study on Energy Overhead of Different IoT Network Stacks2019In: 2019 IEEE 5th World Forum on Internet of Things (WF-IoT), IEEE, 2019, p. 528-529Conference paper (Refereed)
    Abstract [en]

    Due to the limited energy budget for sensor nodes in the Internet of Things (IoT), it is crucial to develop energy efficient communications amongst others. This need leads to the development of various energy-efficient protocols that consider different aspects of the energy status of a node. However, a single protocol covers only one part of the whole stack and savings on one level might not be as efficient for the overall system, if other levels are considered as well. In this paper, we analyze the energy required for an end device to maintain connectivity to the network as well as perform application specific tasks. By integrating the complete stack perspective, we build a more holistic view on the energy consumption and overhead for a wireless sensor node. For better understanding, we compare three different stack variants in a base scenario and add an extended study to evaluate the impact of retransmissions as a robustness mechanism. Our results show, that the overhead introduced by the complete stack has an significant impact on the nodes energy consumption especially if retransmissions are required.

  • 59.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Embedded FPGA memory requirements for real-time video processing applications2005In: 23rd NORCHIP Conference 2005, IEEE conference proceedings, 2005, p. 206-209, article id 1597025Conference paper (Refereed)
    Abstract [en]

    FPGAs show interesting properties for real-time implementation of video processing systems. An important feature is the available on-chip RAM blocks embedded on the FPGAs. This paper presents an analysis of the current and future requirements of video processing systems put on these embedded memory resources. The analysis is performed such that a set of video processing systems are allocated onto different existing and extrapolated FPGA architectures. The analysis shows that FPGAs should support multiple memory sizes to take full advantage of the architecture. These results are valuable for both designers of systems and for planning the development of new FPGA architectures

  • 60.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Design exploration of a multi-camera dome for sky monitoring2016In: ACM International Conference Proceeding Series, Association for Computing Machinery (ACM), 2016, Vol. 12-15-September-2016, p. 14-18, article id 2967419Conference paper (Refereed)
    Abstract [en]

    Sky monitoring has many applications but also many challenges to be addressed before it can be realized. Some of the challenges are cost, energy consumption and complex deployment. One way to address these challenges is to compose a camera dome by grouping cameras that monitor a half sphere of the sky. In this paper, we present a model for design exploration that investigates how characteristics of camera chips and objective lenses affect the overall cost of a node of a camera dome. The investigation showed that by accepting more cameras in a single node can result in a reduced total cost of the system. This concludes that by using suitable design and camera placement technique, a cost-effective solution can be proposed for massive open-area i.e. sky monitoring.

  • 61.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O´Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation2007In: Proceedings - 21st International Parallel and Distributed Processing Symposium, IPDPS 2007; Abstracts and CD-ROM, Long Beach, CA: IEEE conference proceedings, 2007, p. 1-7, article id 4228121Conference paper (Refereed)
    Abstract [en]

    Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have proven to be effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain dataflow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.

  • 62.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation2006In: Proceedings of the FPGA World Conference 2006, 2006Conference paper (Refereed)
    Abstract [en]

    Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have shown to be an effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain data flow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.

  • 63.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems2005In: Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, IEEE conference proceedings, 2005, p. 136-141, article id 1515712Conference paper (Refereed)
    Abstract [en]

    FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.

  • 64.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O´Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Architecture driven memory allocation for FPGA Based Real-Time Video Processing Systems2011In: Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011 2011, Article number 5782639, IEEE conference proceedings, 2011, p. 143-148Conference paper (Refereed)
    Abstract [en]

    In this paper, we present an approach that uses information about the FPGA architecture to achieve optimized allocation of embedded memory in real-time video processing system. A cost function defined in terms of required memory sizes, available block- and distributed-RAM resources is used to motivate the allocation decision. This work is a high-level exploration that generates VHDL RTL modules and synthesis constraint files to specify memory allocation. Results show that the proposed approach achieves appreciable reduction in block RAM usage over previous logic to memory mapping approach at negligible increase in logic usage

  • 65.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Power-aware automatic constraint generation for FPGA based real-time video processing systems2007In: 25th Norchip Conference, NORCHIP, New York: IEEE conference proceedings, 2007, p. 124-128Conference paper (Refereed)
    Abstract [en]

    The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.

  • 66.
    Lawal, Najeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Norell, Håkan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ram allocation algorithm for video processing applications on FPGA2006In: Journal of Circuits, Systems and Computers, ISSN 0218-1266, Vol. 15, no 5, p. 679-699Article in journal (Refereed)
    Abstract [en]

    This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.

  • 67.
    Lepistö, Niklas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Design and Implementation of Video Pre-Processor for FPGA based SoC2008Conference paper (Refereed)
    Abstract [en]

    FPGA based implementation of embedded systems has many attractive characteristics such as: flexibility, low cost, high integration, embedded distributed memories and ex-tensive parallelism. Real-time video processing is an ap-plication area where FPGA based implementations have significant potential. This paper presents the design and implementation of a video pre-processor suitable for use in embedded display applications. Some of the key functions of the pre-processor are cropping and scaling of input video frames and the possibility to use multiple pre-processors in parallel to provide multiple video streams to a display unit

  • 68.
    Lepistö, Niklas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Design and Implemetation of Video Pre-Processor for FPGA based SoCManuscript (Other (popular scientific, debate etc.))
  • 69.
    Lepistö, Niklas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Low-Cost FPGA-based Display Controller Architecture with Embedded Area De-Interlacing FunctionalityManuscript (Refereed)
  • 70.
    Lepistö, Niklas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Design Exploration of Video Pre-Processor for FPGA based SoC2006In: Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics), Berlin: Springer Verlag , 2006, Vol. 3985, p. 87-92Conference paper (Refereed)
    Abstract [en]

    FPGA based implementation of embedded systems has many attractive characteristics such as: flexibility, low cost, high integration, embedded distributed memories and extensive parallelism. One application where there is a significant possible potential for FPGA is for the implementation of real-time video processing. In this paper we present an analysis of a video pre-processor and how this affects the FPGA and RAM resource usage and performance. From these results we indicate the best space-time mapping of operations under different design constraints. These results can be used as a decision base when implementing an FPGA based video enabled display unit.

  • 71.
    Lepistö, Niklas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    High Performance FPGA based Camera Architecture for Range Imaging2005In: 23rd NORCHIP Conference 2005, IEEE conference proceedings, 2005, p. 165-168, article id 1597015Conference paper (Refereed)
    Abstract [en]

    Range imaging is often used in classification of objects in process industry. The speed of inspection needs to be high, so it does not become the bottleneck in the process. This paper presents an FPGA based architecture for range imaging. Using centre of gravity it calculates the range positions from 2D images. The results show that the proposed architecture can process range values with a performance up to 150 Msamples per second. Thus, using cheep standard technology we can achieve up to 3 times higher performance than expensive state-of-the-art high performance smart-cameras.

  • 72.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Abdalla, Suliman
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Evaluation of Mixed-Signal Noise Effects in Photon Counting X-Ray Image Sensor Readout Circuits2006In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, E-ISSN 1872-9576, Vol. 563, no 1, p. 88-91Article in journal (Refereed)
    Abstract [en]

    In readout electronics for photon counting pixel detectors, the tight integration between analog and digital blocks causes the readout electronics to be sensitive to on-chip noise coupling. This noise coupling can result in faulty luminance values in grayscale X-ray images, or as color distortions in a color X-ray imaging system. An exploration of simulating noise coupling in readout circuits is presented which enables the discovery of sensitive blocks at as early a stage as possible, in order to avoid costly design iterations. The photon counting readout system has been simulated for noise coupling in order to highlight the existing problems of noise coupling in X-ray imaging systems. The simulation results suggest that on-chip noise coupling should be considered and simulated in future readout electronics systems for X-ray detectors.

  • 73.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Abdalla, Suliman
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Power Distribution and Substrate Noise Coupling Investigations on the Behavioral Level for Photon Counting Imaging Readout Circuits2007In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, E-ISSN 1872-9576, Vol. 576, no 1, p. 113-117Article in journal (Refereed)
    Abstract [en]

    In modern mixed-signal system design, there are increasing problems associated with noise coupling caused by switching digital parts to sensitive analog parts. As a consequence, there is a growing necessity to understand these problems. In order to avoid costly design iterations, noise coupling simulations should be initiated as early as possible in the design chain. The problems associated with on-chip noise coupling have been discovered in photon counting pixel detector readout systems, where the level of integration of analog and digital circuits is very high on a very small area, and it would appear that these problems will continue to increase for future system designs in this field. This paper deals with the functionality of utilizing behavioral level models for simulating noise coupling in these readout systems. The methods and models are described and simulation results are shown for a photon counting pixel detector readout system.

  • 74.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ytterdal, T.
    Eriksson, P.
    Abdalla, Munir
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A power-line noise coupling estimation methodology for architectural exploration of mixed-signal systems2003In: Proceedings of the Southwest Symposium on Mixed-Signa Design, IEEE Press, 2003, p. 133-137, article id 1190412Conference paper (Refereed)
    Abstract [en]

    This paper presents methods for early estimation of digital to analog noise coupling over the power distribution network in mixed-signal systems. The methods allow both behavioral verification of mixed-signal architectures and their sensitivity to noise coupling of the power distribution network. The behavioral level noise coupling simulation models are implemented as extensions to the SystemC system design language. To illustrate the effectiveness of the proposed methods, we have estimated the power distribution network noise for a photon-counting X-ray pixel array and compared this with SPICE simulations.

  • 75.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ytterdal, Trond
    Eriksson, Patrik
    Abdalla, Munir
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O´Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Behavioral Simulation of Power Line Noise Coupling in Mixed-Signal Systems using SystemC2003In: ISVLSI 2003: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS - NEW TRENDS AND TECHNOLOGIES FOR VLSI SYSTEMS DESIGN, IEEE , 2003, p. 275-277Conference paper (Refereed)
    Abstract [en]

    This paper presents methods for early quantification of digital to analog noise coupling at behavioral level. The methods enable designers to both verify the behavior of their mixed-signal architecture and its sensitivity to noise coupling. The high-level noise coupling simulation models are implemented as extensions to SystemC.

  • 76.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Simulating behavioral level on-chip noise coupling using systemCManuscript (Other academic)
  • 77.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Norlin, Börje
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Abdalla, Suliman
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    An Area Efficient Readout Architecture for Photon Counting Color Imaging2007In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, E-ISSN 1872-9576, Vol. 576, no 1, p. 132-136Article in journal (Refereed)
    Abstract [en]

    The introduction of several energy levels, namely color imaging, in photon counting X-ray image sensors is a trade-off between circuit complexity and spatial resolution. In this paper we propose a pixel architecture that has full resolution for the intensity and uses sub-sampling for the energy spectrum. The results show that this sub-sampling pixel architecture produces images with an image quality which is, on average, 2.4 dB (PSNR) higher than those for a single energy range architecture and with half the circuit complexity of that for a full sampling architecture.

  • 78.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ytterdal, T.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Simplified Gate Level Noise Injection Models for Behavioral Noise Coupling Simulation2005In: Proceedings of the 2005 European Conference on Circuit Theory and Design: 28 Aug.-2 Sept. 2005, Cork, Ireland, Piscataway, NJ, USA: IEEE conference proceedings, 2005, Vol. 3, p. 345-348, article id 1523131Conference paper (Refereed)
    Abstract [en]

    In CMOS digital logic, there are two major noise sources requiring consideration. These are a circuit´s power supply current and its noise current injected into the substrate of the circuit. This paper proposes a method for modeling and estimating the noise current injected into the substrate by capacitive coupling in digital circuits. The simplicity of the model and the reduction of details in the technology libraries facilitates behavioral level noise coupling simulation. The model is exemplified and evaluated for a simple NOT gate test case, for which the accuracy and simplicity of the models show great promise for simulation at the behavioral level.

  • 79.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ytterdal, Trond
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Noise injection models for behavioral level noise coupling simulationManuscript (Other academic)
  • 80.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ytterdal, Trond
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Taking Mixed-Signal Substrate Noise Coupling Simulation to the Behavoral Level using SystemC2004In: Proceedings of the International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2004)), 2004Conference paper (Refereed)
    Abstract [en]

    The paper presents methods and models to simulate substrate noise coupling at the behavioral level. The models are implemented as a part of the SystemC based Behavioral level Noise Coupling (BeNoC) simulation application. The application is designed as a wrapper to SystemC component modules, enabling designers to simulate substrate noise coupling in their modules during the entire circuit refinement process. This is enabled through the two main contributions presented in this paper: (1) methods to connect the behavioral level with low level circuit simulations and (2) generation of a fast and accurate circuit model for substrate coupling simulations. The accuracy of the generated substrate noise coupling model is verified against device simulations. The same verification test case is used to demonstrate the connection between behavioral simulations and circuit simulations.

  • 81.
    Lundgren, Jan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ytterdal, Trond
    Vonbum, Kristian
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Substrate Noise Coupling models for Behavioral Mixed-Signal Simulation in SystemC2004In: Proceedings. 4th IEEE International Workshop on System-on-Chip for Real-Time Applications, (IWSOC'04), 2004, 2004, p. 201-205Conference paper (Refereed)
    Abstract [en]

    We present methods and models to simulate substrate noise coupling at the behavioral level. The models are implemented as a part of the SystemC based Behavioral level Noise Coupling (BeNoC) simulation application. The application is designed as a wrapper to SystemC component modules, enabling designers to simulate substrate noise coupling in their modules during the entire circuit refinement process. This is enabled through the two main contributions presented in this paper: (1) methods to connect the behavioral level with low level circuit simulations and (2) generation of a fast and accurate circuit model for substrate coupling simulations. The accuracy of the generated substrate noise coupling model is verified against device simulations. The same verification test case is used to demonstrate the connection between behavioral simulations and circuit simulations.

  • 82.
    Nordin, Lisa
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Natural Sciences, Engineering and Mathematics.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Engstrand, Per
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Natural Sciences, Engineering and Mathematics.
    Bäck, Roland
    SCA R&D Centre.
    Ferritsius, Olof
    Pöyry Sweden AB.
    Ferritsius, Rita
    Pöyry Sweden AB.
    Sandberg, Christer
    Holmen Paper Development Centre.
    Sundvall, Öjvind
    Eurocon Analyzer AB.
    Analysis of the quality of optical fibre and fines measurement for prediction of dewatering characteristics for mechanical pulpsManuscript (Other academic)
    Abstract [en]

    The quality of the optical fibre and fines measurement has been investigated. Fibres and fines of different quality were mixed in defined proportions and the mixtures were characterized by means of optical fibre measurements and dewatering behaviour. The results show that the same measured fines amounts show different dewatering behaviour, depending on the quality of the fines used. The difference in fines quality was, however, not reflected in the optical measurement. We conclude that this is caused by too low resolution in the optical measurement, so there is a large need for higher resolution of the measurement equipments in order to make it possible to measure the shape of the fines.

  • 83.
    Nordin, Lisa
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Natural Sciences, Engineering and Mathematics.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Engstrand, Per
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Natural Sciences, Engineering and Mathematics.
    Bäck, Roland
    SCA R&D Center.
    Ferritsius, Olof
    Pöyry.
    Sandberg, Christer
    Holmen Paper Development Centre.
    Measurement and prediction of dewatering characteristics for mechanical pulps using optical fibre analyzers2009In: Proceedings - 2009 International Mechanical Pulping Conference, IMPC 2009, 2009, p. 309-316Conference paper (Refereed)
    Abstract [en]

    The aim of this work was to obtain an on-line measurement for dewatering behaviour in the wire section based on fibre and fines characteristics. Four laboratory dewatering equipments were compared and the fibre characteristics were measured by means of optical fibre analyzers.

    The results show that rough correlations do appear to exist between the dewatering equipments; however they rank the pulps differently depending on the raw wood material used and whether the refining conditions are mild or harsh. The prediction models based on fibre characteristics showed a high degree of statistical accuracy. The descriptions, however, proved not to be sufficiently good with regards to the dewatering behaviour for them to be used in relation to on-line applications. This might have been because consideration was not given to some important variables which do, in fact, have a significant impact on the drainability. These variables could include physical fibre properties or others that are not measured, or properties that, at present, are unable to be measured at a sufficient resolution.

  • 84.
    Nordin, Lisa
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Natural Sciences, Engineering and Mathematics.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Engstrand, Per
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Natural Sciences, Engineering and Mathematics.
    Sundvall, Öjvind
    Eurocon Analyzer AB.
    Characterization and classification of dewatering measurement techniques for mechanical pulps2008In: Proceedings of the PRS, Finland, May 2008., 2008Conference paper (Refereed)
  • 85.
    Nordin, Lisa
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O´Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Engstrand, Per
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Sundvall, Öjvind
    Towards relevant dewatering measurement techniques: Caracterisation and classification of dewatering measurement techniques for mechanical pulps2008In: FMPRS May 2008, 2008Conference paper (Refereed)
  • 86.
    Norell, Håkan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Ericsson, A.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Cubic Vector Median Filter for Noise Reduction and Improvement of Compression Efficiency2004In: IWSSIP'04 : international workshop on systems, signals and image processing :   ( Poznan, 13-15 September 2004 ), Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering , 2004Conference paper (Refereed)
    Abstract [en]

    Encoding of image sequences is today a standard task for computers and home entertainment systems. The input material is often of shifting quality, i.e. corrupted by noise in various ways. In order to store the information in an effective way some kind of compression has to be applied. When video compression is applied on an image sequence, the result is sub optimal due to the introduced noise variations. This paper presents a new cubic median filter suitable for pre-processing of noise contaminated video sequences. The presented approach reduces the bit usage for MPEG-2 encoding with up to 62% for impulse noise impaired sequences and 38% for the corresponding Gaussian.

  • 87.
    Norell, Håkan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems2007In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, Vol. 2007, article id 75368Article in journal (Refereed)
    Abstract [en]

    This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

  • 88.
    Norell, Håkan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    VIPS: Video Image Processing In a Second2006Conference paper (Refereed)
  • 89.
    Norell, Håkan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A Generalized Architecture for Hardware Synthesis of Spatio-Temporal Memory Models for Image Processing Systems2005In: IWSSIP 2005 - Proceedings of the 12th International Worshop on Systems, Signals & Image Processing, InderScience Publishers, 2005, p. 361-365Conference paper (Refereed)
    Abstract [en]

    This paper presents a generalized architecture for the synthesis of application specific memory architectures for real-time image processing systems. The memory generation presented in this paper can handle both spatial and spatio-temporal memory models. The results show that the architecture efficiently solves the problems related to memory accesses for most of the available video image processing filters available at present.

  • 90.
    Norell, Håkan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Requirement Analysis of Reconfigurable Hardware Prototyping Platforms for Development of Real-Time Video Applications2000In: Proceedings of 18th IEEE Norchip Conference, 2000Conference paper (Refereed)
  • 91.
    Norell, Håkan
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Automatic Hardware Synthesis of Spatial Memory Models for Real-Time Image Processing Systems2003In: Proceedings of IEEE Norchip Conference 2003: Riga, Latvia, Nov 10-11, 2003, 2003, p. 171-175Conference paper (Refereed)
  • 92.
    Norlin, Börje
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Anna
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Erik
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thungström, Göran
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Energy Resolved X-ray Imaging as a Tool for Characterization of Paper Coating Quality2009In: IEEE Nuclear Science Symposium Conference Record 2009, IEEE conference proceedings, 2009, p. 1703-1706Conference paper (Refereed)
    Abstract [en]

    Energy resolved X-ray imaging can be used as a tool to analyze the variation in the chemical content of an object. In this work we have used energy resolved X-ray imaging to measure the variation in the chemical content of paper and paper coating. This is an important quality parameter for the paper industry. In order to separate the variation in coating thickness from the variation in paper thickness, energy resolution is used to separate the response of the coating from the response of the paper. The MEDIPIX2 single photon processing X-ray imaging system [1] has been used in the measurements.  The measurement results are compared to simulations with MCNP. The influence of charge sharing is discussed and the effects have been studied by comparing results from detectors with 220x220 µm2 pixels and detectors with 55x55 µm2 pixels. There is a trade-off between good spatial resolution obtained with detectors with small pixels and good energy resolution obtained with detectors with large pixels. The requirements on image quality, to achieve the resolution of coating distribution relevant for the application, are discussed.

  • 93.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Abdalla, Munir
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Robust window discriminator for photon-counting pixel detectors2002In: IEE Proceedings - Optoelectronics, ISSN 1350-2433, Vol. 149, no 2, p. 65-69Article in journal (Refereed)
    Abstract [en]

    The paper proposes a robust and area-efficient way of designing window discriminators for photon-counting pixel detectors. For that, an all-digital window discriminator is proposed. It is event-driven and does not rely on any external or internal timing references, which makes it possible to use it over a wide range of specifications. In addition, it provides an overall area efficient implementation of the digital electronics in photon-counting pixel detectors. The transistor-level implementation of the circuit is presented with its circuit area and timing performance.

  • 94.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Abdalla, Suliman
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    All-Digital Window Discriminator for Photon Counting Pixel Detectors2001In: Electronics Letters, ISSN 0013-5194, Vol. 37, no 6, p. 373-374Article in journal (Refereed)
    Abstract [en]

    An all-digital window discriminator is presented. It is event-driven and does not rely on any external or internal timing references. In addition, it provides an area-efficient implementation of photon counting pixel detectors. The transistor-level implementation of the circuit is presented with its circuit area and timing performance.

  • 95.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A Course in Basic Digital Electronics for a Distance Educational Programme2004In: Proceedings of IEEE International Conference on Signals and Electronic Systems, 2004Conference paper (Refereed)
  • 96.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A Low Power Hand-Over Mechanism for Gated-Clock FSMs1999In: Proceedings of the European Conference on Circuit Theory and Design, 1999Conference paper (Refereed)
  • 97.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Asynchronous Control of Low-Power Gated-Clock Finite-State Machines1999In: Proceedings of IEEE International Conference on Electronics, Circuits and Systems, 1999Conference paper (Refereed)
  • 98.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    LIFS: A Tool for Low-Power Implementation of FSMs1999In: Proceedings of the 17th IEEE Norchip Conference, 1999Conference paper (Refereed)
    Abstract [en]

    We present a tool (LIFS) for low-power implementation of finite state machines (FSMs). The tool decomposes a FSM into several small communicating sub state machines (partitions). Low-power operation is achieved since only one partition is active (clocked) at a time, thus fewer registers need to be clocked. The hand-over mechanism between different partitions in the final state machine is controlled by asynchronous controllers. By using an asynchronous hand-over mechanism our approach has up to five times less power overhead than comparable approaches. To show the effectiveness of the LIFS tool, we present experimental results from standard benchmark examples.

  • 99.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Tammemäe, K.
    Kruus, M.
    Tenhunen, H.
    Automatic FSM synthesis for low-power mixed synchronous/asynchronous implementation2000Report (Other scientific)
  • 100.
    Oelmann, Bengt
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Tammenmäe, K.
    Kruus, M.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Automatic FSM synthesis for low-power mixed synchronous/asynchronous implementation2001In: VLSI design (Print), ISSN 1065-514X, E-ISSN 1563-5171, Vol. 12, no 2, p. 167-186Article in journal (Refereed)
    Abstract [en]

    Power consumption in a synchronous FSM (Finite-State Machine) can be reduced by partitioning it into a number of coupled sub-FSMs where only the part that is involved in a state transition is clocked. Automatic synthesis of a partitioned FSM includes a partitioning algorithm and sub-FSM synthesis to an implementation architecture. In this paper, we first introduce an implementation architecture for partitioned FSMs that uses gated-clock technique for disabling idle parts of the circuits and asynchronous controllers for communication between the sub-FSMs. We then describe a new transformation procedure for the sub-FSM. The FSM synthesis flow has been automated in a prototype tool that accepts an FSM specification. The tool generates RT-level VHDL code with identical cycle-to-cycle input/output behaviour in accordance to with the specification. An average power reduction of 45% has been obtained for a set standard FSM benchmarks.

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