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  • 1. Li, J.
    et al.
    Wang, W.
    Li, Y.
    Zhou, N.
    Wang, G.
    Kong, Z.
    Fu, J.
    Yin, X.
    Li, C.
    Wang, X.
    Yang, H.
    Ma, X.
    Han, J.
    Zhang, J.
    Wei, Y.
    Hu, T.
    Yang, T.
    Yin, H.
    Zhu, H.
    Radamson, Henry H.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Study of selective isotropic etching Si1−xGex in process of nanowire transistors2020In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 31, no 1, p. 134-143Article in journal (Refereed)
    Abstract [en]

    On approach towards the end of technology roadmap, a revolutionary approach towards the nanowire transistors is favorable due to the full control of carrier transport. The transistor design moves toward vertically or laterally stacked Gate-All-Around (GAA) where Si or SiGe can be used as channel material. This study presents a novel isotropic inductively coupled plasma (ICP) dry etching of Si1−xGex (0.10 ≤ x ≤ 0.28) in SiGe/Si multilayer structures (MLSs) with high selectivity to Si, SiO2, Si3N4 and SiON which can be applied in advanced 3D transistors and Micro-Electro-Mechanical System (MEMS) in future. The profile of SiGe etching for different thicknesses, compositions and locations in MLSs using dry or wet etch have been studied. A special care has been spent for layer quality of Si, strain relaxation of SiGe layers as well as residual contamination during the etching. In difference with dry etching methods (downstream remote plasma), the conventional ICP source in situ is used where CF4/O2/He gas mixture was used as the etching gas to obtain higher selectivity. Based on the reliability of ICP technique a range of etching rate 25–50 nm/min can be obtained for accurate isotropic etching of Si1−xGex, to form cavity in advanced 3D transistor processes in future.

  • 2.
    Liu, Jinbiao
    et al.
    Chinese Academy of Sciences, Beijing, China.
    Wang, Guilei
    Chinese Academy of Sciences, Beijing, China.
    Li, Junfeng
    Chinese Academy of Sciences, Beijing, China.
    Kong, Zhenzhen
    Chinese Academy of Sciences, Beijing, China.
    Radamson, Henry H.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Chinese Academy of Sciences, Beijing, China.
    Study of n-type doping in germanium by temperature based PF+ implantation2020In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 31, p. 161-166Article in journal (Refereed)
    Abstract [en]

    Incorporation of P in germanium was studied by using PF+ molecular implantation in a range from room temperature to 400 °C. The presence of F acted as a barrier for P in-diffusion and resulted in higher activation of P at room temperature. In addition, it is found that when the implantation is performed at 400 °C, the residual defects are stable and the diffusion of P can be blocked during activation annealing. Therefore, the final junction depth could be well controlled by the implantation process itself. This method is meaningful for the shallow junction formation in sub 14-nm Ge-based FinFETs or high-performance photodetectors. 

  • 3.
    Lixing, Zhou
    et al.
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Xiaolei, Wang
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Kai, Han
    Dept. of Phys. & Electron. Sci., Weifang Univ., Weifang, China.
    Xueli, Ma
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Yanrong, Wang
    Microelectron. Dept., North China Univ. of Technol., Beijing, China.
    Jinjuan, Xiang
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Hong, Yang
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Jing, Zhang
    Microelectron. Dept., North China Univ. of Technol., Beijing, China.
    Chao, Zhao
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Tianchun, Ye
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Radamson, Henry H.
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Wenwu, Wang
    Key Lab. of Microelectron. Devices & Integrated Technol., Inst. of Microelectron., Beijing, China.
    Understanding dipole formation at dielectric/dielectric hetero-interface2018In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 113, no 18, article id 0003-6951Article in journal (Refereed)
    Abstract [en]

    Band alignment and dipole formation at the hetero-interface still remain fascinating and, hence, are being intensively investigated. In this study, we experimentally investigate the dipole formation by employing a dielectric/dielectric (Al2O3/GeO2) interface. We investigate the dipole dependence on various post-deposition annealing (PDA) ambiences from the viewpoints of electrical extraction and the X-ray photoelectron spectroscopy measurement. The core level shift at the Al2O3/GeO2 interface is consistent with the dipole changes in various PDA ambiences. We discover that the dipole formation can be well explained by the interface gap state and charge neutrality level theory. These results further confirm the feasibility of gap state theory in explaining the band alignment at hetero-junctions. This study can be a booster to enhance the comprehension of dipole origin at hetero-junction interfaces.

  • 4.
    Qin, C.
    et al.
    Chinese Academy of Sciences, Beijing, China.
    Yin, H.
    Chinese Academy of Sciences, Beijing, China.
    Wang, G.
    Chinese Academy of Sciences, Beijing, China.
    Zhang, Y.
    Chinese Academy of Sciences, Beijing, China.
    Liu, J.
    Chinese Academy of Sciences, Beijing, China.
    Zhang, Q.
    Chinese Academy of Sciences, Beijing, China.
    Zhu, H.
    Chinese Academy of Sciences, Beijing, China.
    Zhao, C.
    Chinese Academy of Sciences, Beijing, China.
    Radamson, Henry H.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Chinese Academy of Sciences, Beijing, China.
    A novel method for source/drain ion implantation for 20 nm FinFETs and beyond2020In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 31, p. 98-104Article in journal (Refereed)
    Abstract [en]

    This paper presents a method to improve source/drain extension (SDE) ion implantation (I/I) process for sub-20 nm node FinFETs with no extra step in transistor process. Traditionally, SDE I/I process needs a large implant tilt angle and a high dose to obtain a heavy and conformal doping. However, this process leads to implantation shadow effects and Si-fin amorphization. These drawbacks can be removed in our new approach when SDE I/I is modified and moved after S/D epitaxy process (SDE I/I-last). Because of the facet planes of the SiGe layer, the ions are allowed to be implanted with small tilt. This is helpful to avoid shadow effects of implantation and to keep the low defect density in the S/D. As a result, the external resistance (R EXTRNL ) is not high and the strain relaxation is minor in S/D epitaxy layer. Finally, p-type FinFETs with 25 nm gate length with SDE I/I-last are fabricated. These new FinFETs demonstrate ~ 50% on-state current (I ON ) improvement compared to those transistors fabricated by traditional method.

  • 5.
    Radamson, Henry H.
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    He, Xiaobin
    Chinese Acad Sci, Beijing, Peoples R China.
    Zhang, Qingzhu
    Chinese Acad Sci, Beijing, Peoples R China; Gen Res Inst Nonferrous Met, Beijing, Peoples R China.
    Liu, Jonbiao
    Chinese Acad Sci, Beijing, Peoples R China.
    Cui, Hushan
    Beihang Univ, BDBC, Beijing, Peoples R China.
    Xiang, Jinjuan
    Chinese Acad Sci, Beijing, Peoples R China.
    Kong, Zhenzhen
    Chinese Acad Sci, Beijing, Peoples R China.
    Xiong, Wenjuan
    Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    Li, Junjie
    Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    Gao, Jianfeng
    Chinese Acad Sci, Beijing, Peoples R China.
    Yang, Hong
    Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    Gu, Shihai
    Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    Zhao, Xuewei
    Chinese Acad Sci, Beijing, Peoples R China; Univ Sci & Technol China, Hefei, Anhui, Peoples R China.
    Du, Yong
    Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    Yu, Jiahan
    Chinese Acad Sci, Beijing, Peoples R China.
    Wang, Guilei
    Chinese Acad Sci, Beijing, Peoples R China; Univ Chinese Acad Sci, Beijing, Peoples R China.
    Miniaturization of CMOS2019In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 10, no 5, article id 293Article in journal (Refereed)
    Abstract [en]

    When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

  • 6.
    Wang, Guilei
    et al.
    Chinese Academy of Sciences, Beijing, China.
    Kolahdouz, M.
    University of Tehran, Tehran, Iran.
    Luo, Jun
    Chinese Academy of Sciences, Beijing, China.
    Qin, Changliang
    Chinese Academy of Sciences, Beijing, China.
    Gu, Shihai
    Chinese Academy of Sciences, Beijing, China.
    Kong, Zhenzhen
    Chinese Academy of Sciences, Beijing, China.
    Yin, Xiaogen
    Chinese Academy of Sciences, Beijing, China.
    Xiong, Wenjuan
    Chinese Academy of Sciences, Beijing, China.
    Zhao, Xuewei
    Chinese Academy of Sciences, Beijing, China.
    Liu, Jinbiao
    Chinese Academy of Sciences, Beijing, China.
    Yang, Tao
    Chinese Academy of Sciences, Beijing, China.
    Li, Junfeng
    Chinese Academy of Sciences, Beijing, China.
    Yin, Huaxiang
    Chinese Academy of Sciences, Beijing, China.
    Zhu, Huilong
    Chinese Academy of Sciences, Beijing, China.
    Wang, Wenwu
    Chinese Academy of Sciences, Beijing, China.
    Zhao, Chao
    Chinese Academy of Sciences, Beijing, China.
    Ye, Tianchun
    Chinese Academy of Sciences, Beijing, China.
    Radamson, Henry H.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Chinese Academy of Sciences, Beijing, China.
    Growth of SiGe layers in source and drain regions for 10 nm node complementary metal-oxide semiconductor (CMOS)2020In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 31, p. 26-33Article in journal (Refereed)
    Abstract [en]

    In this study, the integration of Si 1−x Ge x (50% ≤ x ≤ 60%) selective epitaxy on source/drain regions in 10 nm node FinFET has been presented. One of the major process issues was the sensitivity of Si-fins’ shape to ex- and in-situ cleaning prior to epitaxy. For example, the sharpness of Si-fins could easily be damaged during the wafer washing. The results showed that a DHF dip before the normal cleaning, was essential to clean the Si-fins while in-situ annealing in range of 780–800 °C was needed to remove the native oxide for high epitaxial quality. Because of smallness of fins, the induced strain by SiGe could not be directly measured by X-ray beam in a typical XRD tool in the lab or even in a Synchrotron facility. Further analysis using nano-beam diffraction technique in high-resolution transmission electron microscope also failed to provide information about strain in the FinFET structure. Therefore, the induced strain by SiGe was simulated by technology computer-aided design program and the Ge content was measured by using energy dispersive spectroscopy. Simulation results showed 0.8, 1 and 1.3 GPa for Ge content of 40%, 50% and 60%, respectively. A kinetic gas model was also introduced to predict the SiGe profile on Si-fins with sharp triangular shape. The input parameters in the model includes growth temperature, partial pressure of the reactant gases and the exposed Si coverage in the chip area.

  • 7.
    Xiong, Wenjuan
    et al.
    Chinese Academy of Sciences, Beijing, China; University of Chinese Academy of Sciences, Beijing, China.
    Jiang, Haojie
    Chinese Academy of Sciences, Beijing, China.
    Li, Tingting
    Chinese Academy of Sciences, Beijing, China.
    Zhang, Peng
    Chinese Academy of Sciences, Beijing, China.
    Xu, Qing
    Chinese Academy of Sciences, Beijing, China; University of Science and Technology of China, Hefei, People’s Republic of China.
    Zhao, Xuewei
    Chinese Academy of Sciences, Beijing, China; University of Science and Technology of China, Hefei, People’s Republic of China.
    Wang, Guilei
    Chinese Academy of Sciences, Beijing, China.
    Liu, Yaodong
    Chinese Academy of Sciences, Beijing, China.
    Luo, Ying
    Chinese Academy of Sciences, Beijing, China.
    Li, Zhihua
    Chinese Academy of Sciences, Beijing, China.
    Li, Junfeng
    Chinese Academy of Sciences, Beijing, China.
    Yu, Jinzhong
    Chinese Academy of Sciences, Beijing, China.
    Chao, Zhao
    Chinese Academy of Sciences, Beijing, China.
    Wang, Wenwu
    Chinese Academy of Sciences, Beijing, China.
    Radamson, Henry H.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Chinese Academy of Sciences, Beijing, China; University of Chinese Academy of Sciences, Beijing, People’s Republic of China.
    SiNx films and membranes for photonic and MEMS applications2020In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 31, p. 90-97Article in journal (Refereed)
    Abstract [en]

    This work presents a novel process to form SiN x films and process for membranes with excellent mechanical properties for micro-electro-mechanical systems application as well as integration as IR waveguide for photonic application. The SiN x films were fabricated in SiNgen apparatus which is a single wafer chamber equipment compared to conventional low pressure chemical vapor deposition furnace process. The films showed low stress, good mechanical properties, but the synthesis also eradicates the issues of particle contamination. Through optimizing of the growth parameters and post annealing profile, low stress (40 Mpa) SiN x film could be finally deposited when annealing temperature rose up to 1150 °C. The stress relaxation is a result of more Si nano-crystalline which was formed during annealing, according to the FTIR results. The mechanical properties, Young’s modulus and hardness, were 210 Gpa and 20 Gpa respectively. For the waveguide application, a stack of three layers, SiO 2 /SiN x /SiO 2 was formed where the optimized layer thicknesses were used for minimum optical loss according to simulation feedback. After deposition of the first two layers in the stack, the samples were annealed in range of 900–1150 °C in order to release the stress. Chemical mechanical polish technique was applied to planarize the nitride layer prior to the oxide cladding layer. Such wafers can be used to bond to Si or Ge to manufacture advanced substrates.

  • 8.
    Zhao, Xuewei
    et al.
    University of Science and Technology of China, Hefei, Anhui, China; Chinese Academy of Sciences, Beijing, China.
    Moeen, M.
    KTH Royal Institute of Technology, Stockholm.
    Toprak, M. S.
    KTH Royal Institute of Technology, Stockholm.
    Wang, G.
    Chinese Academy of Sciences, Beijing, China.
    Luo, J.
    Chinese Academy of Sciences, Beijing, China.
    Ke, X.
    Chinese Academy of Sciences, Beijing, China.
    Li, Z.
    Chinese Academy of Sciences, Beijing, China.
    Liu, D.
    Chinese Academy of Sciences, Beijing, China.
    Wang, W.
    Chinese Academy of Sciences, Beijing, China.
    Zhao, C.
    Chinese Academy of Sciences, Beijing, China.
    Radamson, Henry H.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Chinese Academy of Sciences, Beijing, China.
    Design impact on the performance of Ge PIN photodetectors2020In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 31, p. 18-25Article in journal (Refereed)
    Abstract [en]

    This article presents the impact of epitaxial quality, contact resistance and profile of Ge PIN photodetectors (PDs) on dark current and responsivity. The PD structures were processed with either selectively grown Ge with integrated waveguides on SOI wafer or globally grown Ge on the entire wafer. The contact resistance was lowered by introducing NiGe layer prior to the metallization. The n-type doped Ge PIN structure was formed by ion implantation and the contact resistivity was estimated to 2.6 × 10 −4  Ω cm 2 . This value is rather high and it is believed to be due to fomation of defects during implantation. The results show a minor difference in dark currents for selectively and globally grown PDs but in both types, it depends on detector area and the epitaxial quality of Ge. For example, the threading dislocation density (TDD) in non-selectively grown PDs with thickness of 1 µm was estimated to be 10 6  cm −2 yielding relatively low dark currents while it dramatically changes for PDs with thinner Ge layers where TDD increases to 10 8  cm −2 and the dark current levels increase almost by 1.5 magnitude. Surprisingly, for selectively grown PDs with Ge thickness of 500 nm, TDD was still low resulting in low dark currents. The dark current densities at − 1 V bias of non-selectively and selectively grown PDs with optimized profile were measured to be 5 mA/cm 2 and 47 mA/cm 2 , respectively, while the responsivity of these detectors were 0.17 A/W and 0.46 A/W at λ ~ 1.55 µm, respectively. Excellent performance for selectively grown PD shows an appropriate choice for detection of 1.55 µm wavelength. 

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