miun.sePublications
Change search
Refine search result
1 - 12 of 12
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Rows per page
  • 5
  • 10
  • 20
  • 50
  • 100
  • 250
Sort
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
  • Standard (Relevance)
  • Author A-Ö
  • Author Ö-A
  • Title A-Ö
  • Title Ö-A
  • Publication type A-Ö
  • Publication type Ö-A
  • Issued (Oldest first)
  • Issued (Newest first)
  • Created (Oldest first)
  • Created (Newest first)
  • Last updated (Oldest first)
  • Last updated (Newest first)
  • Disputation date (earliest first)
  • Disputation date (latest first)
Select
The maximal number of hits you can export is 250. When you want to export more records please use the Create feeds function.
  • 1.
    Alfredsson, Jon
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Design of a Parallel A/D-converter System on PCB - For High-Speed Sampling and Timing Error Correction: Examensarbete - Linköpings universitet2002Other (Other academic)
    Abstract [en]

    The goals for most of today´s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with �state-of-the-art� components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system�s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvements to achieve even higher performance.

  • 2.
    Alfredsson, Jon
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies2008Doctoral thesis, comprehensive summary (Other scientific)
  • 3.
    Alfredsson, Jon
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages2007Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    All who is involved in electronic design knows that one of the critical issues

    in today’s electronic is the power consumption. Designers are always looking for

    new approaches in order to reduce currents while still retain performance.

    Floating-gate (FGMOS) circuits have previously been shown to be a promising

    technique to improve speed and still keep the power consumption low when

    power supply is reduced below subthreshold voltage for the transistors.

    In this thesis, the goal is to determine how good floating-gate circuits can be

    compared to conventional static CMOS when the circuits are working in

    subthreshold. The most interesting performance parameters are speed and power

    consumption and specifically the Energy-Delay Product (EDP) that is a

    combination of those two. To get a view over how the performance varies and how

    good the FGMOS circuits are at their best case, the circuits have been designed and

    simulated for best case performance.

    The investigation also includes trade-offs with speed and power

    consumption for better performance, how to select floating-gate capacitances, how

    a large circuit fan-in will affect performance and also the influence of different

    kinds of refresh circuits.

    The first simulations of the FGMOS circuits in a 0.13 μm process have

    several interesting results. First of all, in the best case it is shown that FGMOS has

    potential to achieve up to 260 times in better EDP-performance compared to CMOS

    at 150 mV power supply. Continuing with simulations of FGMOS capacitances

    shows that minimum floating-gate capacitance can be as small as 400 fF and more

    realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

    capacitances included). Other aspects of FGMOS design have been to look at how

    refresh circuits will affect performance (semi-floating-gate circuits) and how a

    larger fan-in will change noise margin and EDP. It turns out that refresh circuits

    with the same transistor size does not give a noticeable change in performance

    while an increase of 8 times in size will give between 5 and 10 times wors EDP.

    When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

    possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

    150 mV.

    Finally, it should be kept in mind that tuning the performance of FGMOS

    circuits with trade-offs and by changing the floating-gate voltages to achieve

    results like the ones stated above will also always affect the noise margins, NM, of

    the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

    fabricated circuit with that NM may not be as functional as simulations suggests.

    The probability to design functional FGMOS circuits in subthreshold does not

    seem to be a problem though.

  • 4.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements2007In: 2007 NORCHIP, IEEE conference proceedings, 2007, p. 146-149Conference paper (Refereed)
    Abstract [en]

    When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

  • 5.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply2007In: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Berlin: Springer, 2007, p. 536-546Conference paper (Refereed)
    Abstract [en]

    To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

  • 6.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Pseudo floating-gate design limitations in Nano-CMOS with low power supply2008In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008, 2008Conference paper (Refereed)
    Abstract [en]

    This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.

     

  • 7.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations2008In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008, 2008Conference paper (Refereed)
    Abstract [en]

    The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.

     

  • 8.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold2005In: Proceedings of IFIP VLSI-SOC 2005: International Conference on Very Large Scale Integration, Edith Cowan Univ , 2005, p. 229-232Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

  • 9.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure2007In: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, IEEE conference proceedings, 2007, p. 314-317Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

  • 10.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold2006In: Proceedings - IEEE International Symposium on Circuits and Systems, IEEE conference proceedings, 2006, p. 4341-4344, article id 1693590Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

  • 11.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs2006In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 1296-1299Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

  • 12.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Trading Speed and Power for Reduced Substrate Noise from Digital CMOS Circuits2004In: Proceedings of IEEE International Conference on Signals and Electronic Systems, Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering , 2004Conference paper (Refereed)
1 - 12 of 12
CiteExportLink to result list
Permanent link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf