Mid Sweden University

This study is an investigation of how members of the Norwegian and the Swedish parliaments relate to and perceive their relationships with the media. Based on surveys conducted among members of the Norwegian Storting and the Swedish Riksdag, we find that male MPs have more frequent and somewhat less formal relationships with media and journalists compared with female MPs. The results also suggest that male MPs have adapted to the media and their logic more than female MPs. Female MPs also appear to be more critical towards the requirements imposed on politicians who want to get media exposure, compared with male MPs. Analysis reveals that gender differences are smaller among Swedish than Norwegian MPs.

A key concept in research on the media coverage of politics is the game or strategy frame. Contrasted with coverage of politics as issues, theframing of politics as a strategic game is marked by features such as winning and losing as the central concern and a focus on how candidates or parties are doing in opinion polls. The pervasiveness of such framing is, however, disputed since (1) the way in which the frames are conceptualized and operationalized differs significantly; and (2) while some use terms such as 'game frame' and 'strategy frame' as synonymous, others argue that there is a conceptual difference between them. Against this background, this article reviews research on the media's framing ofpolitics as a strategic game, what concepts have been used, and how they have been operationalized; and suggests a synthesis and ways of improving conceptual clarity and comparability in research on the media's use of strategy and/or game frames. © SAGE Publications 2011.

The investigation was initiated because of the high workload of the sellers and, additionally, because the Tunadal sawmill has received low ratings in customer surveys. Thus,  two main approaches are adopted here,  the first being to investigate which of the three methods  of working, namely, market divided flow organization, function organizationand flow organization with collaboration, proves to be the most beneficial. The second is to investigate whether there is an available method to ease the daily work. A literature review has been made in order to determine more efficient ways for the sellers to work in the Tunadal sawmill. During the investigation, an in-depth investigation into the total quality management using a balanced scorecard as a management tool was conducted. To identify the current problems, interviews and workshops were conducted with the department members. A customer survey was sent to the customers in order to obtain some indication in relation to their opinions. The results showed that there are many unnecessary working operations such as control, duplication of work and problem solving. Communication between the various departments and individuals proved to sometimes be poor.  A major reason for the sellers’ problems regarding workload was due to the unavailability of goods on the discharge date. Many benefits are associated with the collaborative flow organization as this increases the holistic view and can assist in relation to communication. The function based method of working would, however, lead to greater isolation of the functions in the business. Very little work regarding identification of problems that occur in the processes exists and focus on working with improvements is limited. It would be advantageous to work with total quality management using the balanced scorecard as a management tool in the flow organization based on cooperation as this also promotes the holistic approach.

Keywords:Efficiency improvement, total quality management, balanced

In this paper we present an integrating CMOS Active Pixel Sensor (APS) circuit to be used with scintillator type X-ray sensors for intra oral dental X-ray imaging systems. Different pixel architectures were constructed to explore their performance characteristics and to study the feasibility of the development of such systems using the CMOS technology. A prototype 64×80 pixel array has been implemented in a CMOS 0.8 μm double poly n-well process with a pixel pitch of 50 μm. A spectral sensitivity measurement for the different pixels topologies, as well as measured X-ray direct absorption in the different APSs are presented. A measurement of the output signal showed a good linearity over a wide dynamic range. This chip showed that the very low sensitivity of the CMOS APSs to direct X-ray exposure adds a great advantage to the various CMOS advantages over CCD-based imaging systems.

We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 32 x 80 element CMOS active pixel array was implemented in a 0.8 mum CMOS double poly, n-well process with a pixel pitch of 50 mum. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

Hybrid pixel array detectors for X-ray imaging are based on different technologies for sensor and readout electronics. The readout electronics are based on standard CMOS technologies that are experiencing continuously rapid improvements by means of down-scaling the feature sizes, which in turn lead to higher transistor densities, lower power consumption, and faster circuits. For pixel-array imaging sensors the improvements in CMOS technology opens up new possibilities of integrating more functionality in the pixels for local processing of the sensor data. However, new issues related to the tight integration of both analog and digital processing circuits within the small area of a pixel must also be evaluated.

The advantages of down-scaling the CMOS technology can be utilized to increase the spatial resolution by reducing the pixel sizes. Recent research indicates however that the bottleneck in reaching further spatial resolution in X-ray imaging sensors may not be limited by the circuit area occupied by the functions necessary in the pixels, but are instead related to problems associated with charge-sharing of charges generated by the sensor which are distributed over a neighbourhood of pixels and will limit the spatial resolution and lead to a distortion of the energy spectrum. In this thesis a mechanism to be implemented in the readout circuits is proposed in order to suppress the charge-sharing effects. The proposed architecture and its circuit implementation are evaluated with respect to circuit complexity (area) and power consumption. For a photon-counting pixel it is demonstrated that the complete pixel, with charge-sharing suppression mechanism, can be implemented using 300 transistors with an idle power consumption of 2.7μW in a 120nm CMOS technology operating with a 1.2V power supply.

The improvements in CMOS technology can also be used for increasing the range of applications for X-ray imaging sensors. In this thesis, an architecture is proposed for multiple energy discrimination, called color X-ray imaging. The proposed solution is the result of balancing the circuit complexity and the image quality. The method is based on color sub-sampling with intensity biasing. For three-level energy discrimination, that corresponds to color imaging systems for visible light with R, G, and B color components, the increase in circuit complexity will be only 20% higher than that for the Bayer method but results in significantly better image quality.

As the circuit complexity in the digital processing within each pixel is increased, the digitally induced noise may play an increasingly important role for the signal-to-noise ratio in the measurements. In this thesis an initial study is conducted regarding how the digital switching noise affects the analog amplifiers in the photon-counting pixel.

This work proposes an efficient circuit implementation of a mechanism for charge-sharing suppression in photon-counting pixel arrays based on current-mode circuits for the analog parts. The additional circuits needed for charge-sharing suppression in a four-pixel cluster, leads to an increase in power consumption of 36% and only a marginal increase in circuit area. The implemented pixel with window-discrimination, managing charge-sharing in a four-pixel cluster and with an event-counter of 13 bits, consists of 300 transistors and has a power consumption of 2.7 μW when idle. It is implemented in a 120nm CMOS process and the presented results are based on simulations.

This paper proposes an area- and power-efficient implementation of the read-out electronics for color X-ray pixel detectors for imaging. Introducing multiple levels of energy discrimination will increase the complexity of the read-out electronics in each pixel. The proposed architecture has full resolution for the intensity and reduced resolution for the energy spectrum (color), which leads to a good compromise of image quality and circuit complexity. We show that the increase in complexity, compared to single energy-range pixel, will lead to increase in circuit area of less than 20%.

This paper describes a generalized architecture for real-time component labeling and computation of image component features. Computing real-time image component features is one of the most important paradigms for modern machine vision systems. Embedded machine vision systems demand robust performance, power efficiency as well as minimum area utilization. The presented architecture can easily be extended with additional modules for parallel computation of arbitrary image component features. Hardware modules for component labeling and feature calculation run in parallel. This modularization makes the architecture suitable for design automation. Our architecture is capable of processing 390 video frames per second of size 640x480 pixels. Dynamic power consumption is 24.20mW at 86 frames per second on a Xilinx Spartran6 FPGA.

Interpretation and assimilation of data structures, organized information andsource code files are frequently occuring during software development. This kindof information is stored in text-based form and its understanding requires greatthoroughness and investment in time from the developer's part. This thesisdescribes the development of a utility program prototype, which automates theparsing of XML data and source code files from the programming languages Cand C++, in purpose of trying to simplify the interpretation process. The programcreates and presents a visual graph of the structure found, using an algorithmwhich can present arbitrary large XML files as well as a limited number ofconcurrent source code files. The effects on the interpretation time and itsreliablity has been evaluated in a survey among software development students.The result showed a certain increase in the number of correct conclusions fromthe participants' side after studying the visual representation compared to itsorignial text-based form. The amount of time used was not measured other thansubjectively by the users themselves, of which a predominant proportionconsidered a reduction in needed time when using the graphical representation.The thesis shows that the use of this or an equivalent utility can enhance theassimilation of data structures by increasing the rate of reliabilty whilesimultaneously decreasing the needed amount of time. Still, the quantifyable gainsof these results remains statistically largely uncertain.

The purpose of this study was to address the evaluation phase within the area of public procurement and more specifically, from a supplier perspective. Public procurement is carried out in order to get good quality at a low price. The procurement can be performed by the lowest price or by the most economically advantageous tender. Previously concluded contracts were requested and the evaluation model that they used was identified and also it’s corresponding mathematical model. The score-weighted models were not consistent because they depended on irrelevant variables, as did the relative quality-weighted model in theory. This means that non-competitive tender affects the outcome of the other tenders. The study showed that it is more beneficial to choose the relative quality-weighted model over the score-weighting model, as it does not suffer from the irrelevant variable situation. The relative quality-weighted model is equivalent to the more superior quality-weighted model with discrete premium/discounts. This is the case as the ranking of the tenderers bids were the same in the two models. Furthermore, it was shown through a sensitivity analysis, that the weighting for the quality and the price from the score-weighted model played no role in the relative quality-weighted model; this is also an advantage as the purchaser often arbitrarily sets it.

The purpose of this thesis was to investigate if Swedish agencies preserve their websites according to the Swedish archival legislations and guidelines. As a theory the OAIS Reference Model (Open Archival Information System, developed by US Consultative Committee for Space Data Systems, CCSDS) has been used as a model to show how important it is to develop strategies for public digital information which has to be preserved for long term. The ingest function in the OAIS Reference Model demands that files are prepared for long term preservation and requires that the digital information fulfils established technical requirements.

In the study the Swedish National Archive and their advices about preserving websites to archivists on the Swedish agencies are being studied. To control if the agencies meet the requirements for their management and preservation of their websites a survey was sent out to investigate if Swedish agencies preserve their websites.

According to the survey result, 84 of 113 agencies preserve their websites in some way. If the technical requirements really was met could not be verified in this thesis, the results was relied on the responses from the authorities. The study showed that agencies requested clearer rules in the field of preservation of websites, but also that some agencies wasn’t aware of the regulations and the significance in this issue.

The conclusion of the study is that the agencies might need to update themselves on important legislation and guidance in this area. The study also shows that the National Archive must be clearer with their information on long term storage of government agencies websites.

While information technology enables us to access more material than ever before, we need to come to grips with the disagreeable fact that data is not information. Sharing data without safeguarding comprehension may lead to confusion at best and disaster at worst. The issue at hand is one of ensuring semantic interoperability between actors from disparate contexts. Research into this problem is plentiful, but typically focused around specific subject matters, limiting its appeal to a limited range of scholars and practitioners. Based upon a literary study, we identify two extreme approaches to managing semantic interoperability. These are denoted top-down and bottom-up. We illustrate real world instances of these approaches using the TFI-model based on a case study encompassing two organizations. Our theoretical model is found to be a viable lens through which to generalize and interpret issues pertaining to semantic interoperability between human actors. We therefore see a need for further research into human-based on semantic interoperability.

A Visual Sensor Network (VSN) is a distributed system of a largenumber of camera sensor nodes. The main components of a camera sensornode are image sensor, embedded processor, wireless transceiver and energysupply. The major difference between a VSN and an ordinary sensor networkis that a VSN generates two dimensional data in the form of an image, whichcan be exploited in many useful applications. Some of the potentialapplication examples of VSNs include environment monitoring, surveillance,structural monitoring, traffic monitoring, and industrial automation.However, the VSNs also raise new challenges. They generate large amount ofdata which require higher processing powers, large bandwidth requirementsand more energy resources but the main constraint is that the VSN nodes arelimited in these resources.This research focuses on the development of a VSN model to track thelarge birds such as Golden Eagle in the sky. The model explores a number ofcamera sensors along with optics such as lens of suitable focal length whichensures a minimum required resolution of a bird, flying at the highestaltitude. The combination of a camera sensor and a lens formulate amonitoring node. The camera node model is used to optimize the placementof the nodes for full coverage of a given area above a required lower altitude.The model also presents the solution to minimize the cost (number of sensornodes) to fully cover a given area between the two required extremes, higherand lower altitudes, in terms of camera sensor, lens focal length, camera nodeplacement and actual number of nodes for sky surveillance.The area covered by a VSN can be increased by increasing the highermonitoring altitude and/or decreasing the lower monitoring altitude.However, it also increases the cost of the VSN. The desirable objective is toincrease the covered area but decrease the cost. This objective is achieved byusing optimization techniques to design a heterogeneous VSN. The core ideais to divide a given monitoring range of altitudes into a number of sub-rangesof altitudes. The sub-ranges of monitoring altitudes are covered by individualsub VSNs, the VSN1 covers the lower sub-range of altitudes, the VSN2 coversthe next higher sub-range of altitudes and so on, such that a minimum cost isused to monitor a given area.To verify the concepts, developed to design the VSN model, and theoptimization techniques to decrease the VSN cost, the measurements areperformed with actual cameras and optics. The laptop machines are used withthe camera nodes as data storage and analysis platforms. The area coverage ismeasured at the desired lower altitude limits of homogeneous as well asheterogeneous VSNs and verified for 100% coverage. Similarly, the minimumresolution is measured at the desired higher altitude limits of homogeneous aswell as heterogeneous VSNs to ensure that the models are able to track thebird at these highest altitudes.

A Visual Sensor Network (VSN) is a network of spatially distributed cameras. The primary difference between VSN and other type of sensor network is the nature and volume of information. A VSN generally consists of cameras, communication, storage and central computer, where image data from multiple cameras is processed and fused. In this paper, we use optimization techniques to reduce the cost as derived by a model of a VSN to track large birds, such as Golden Eagle, in the sky. The core idea is to divide a given monitoring range of altitudes into a number of sub-ranges of altitudes. The sub-ranges of altitudes are monitored by individual VSNs, VSN1 monitors lower range, VSN2 monitors next higher and so on, such that a minimum cost is used to monitor a given area. The VSNs may use similar or different types of cameras but different optical components, thus, forming a heterogeneous network.  We have calculated the cost required to cover a given area by considering an altitudes range as single element and also by dividing it into sub-ranges. To cover a given area with given altitudes range, with a single VSN requires 694 camera nodes in comparison to dividing this range into sub-ranges of altitudes, which requires only 96 nodes, which is 86% reduction in the cost.

Visual Sensor Networks (VSNs) are networks which generate two dimensional data. The major difference between VSN and ordinary sensor network is the large amount of data. In VSN, a large number of camera nodes form a distributed system which can be deployed in many potential applications. In this paper we present a model of the physical parameters of a visual sensor network to track large birds, such as Golden Eagle, in the sky. The developed model is used to optimize the placement of the camera nodes in the VSN. A camera node is modeled as a function of its field of view, which is derived by the combination of the lens focal length and camera sensor. From the field of view and resolution of the sensor, a model for full coverage between two altitude limits has been developed. We show that the model can be used to minimize the number of sensor nodes for any given camera sensor, by exploring the focal lengths that both give full coverage and meet the minimum object size requirement. For the case of large bird surveillance we achieve 100% coverage for relevant altitudes using 20 camera nodes per km² for the investigated camera sensors.

Since the approval of the IEEE 802.11b by the IEEE in 1999, the demand for WLAN equipment and networks has been growing quickly. We present a queuing model of wireless LAN (WLAN) access points (APs) for IEEE 802.11b. We use experimentation to obtain the characteristic parameters of our analytic model. The model can be used to compare the performance of different WLAN APs as well as the QoS of different applications in the presence of an AP. We focus on the delay introduced by an AP. The major observations are that the delay to serve a packet going from the WLAN medium to the wired medium (on the uplink) is less than the delay to serve a packet, with identical payload, but travelling from the wired medium to the WLAN medium (on the downlink). A key result is an analytic solution showing that the average service time of a packet is a strictly increasing function of payload.

Within both the paper and paperboard industries, real time monitoring and measurement of surface roughness of a paper moving at high velocities is an important and challenging area of research. The uniform surface, for an entire production, can be effectively achieved by monitoring and controlling the paper surface roughness, in real time during the manufacturing steps. Presently the majority of paper industries rely on traditional laboratory profilometers. The obvious limitations of lab profilometers are that these are slow, do not measure the quality of entire reels but rather deal with only a few small pieces of samples taken from the end of the reels and it is difficult to make any possible correction in the productionlines without knowing the online roughness data. To eradicate the disadvantages associated with conventional measurements, an online prototype instrument has been developed that measures the surface roughness during the manufacturing steps, and is based on a line of lighttriangulation technique. The prototype technique will be of assistance in ensuring tight process control in order to maintain both a better and auniform quality throughout the entire production. It measures the whole reel, meter by meter, in traditional units of roughness and is also capable of characterizing the topography in a wide range of wavelength spectra. The article presents the online analyses results obtained from the developed prototype. The real time measurements, in a paperboard pilot mill, have successfully characterized and distinguished 16 different grades of newspaper and paperboard reels including reels which have the same family of quality grades and materials.

In the paper industry, surface topography is the essence of both paper and paperboard, and accurate topographical measurements are equally essential in order to achieve a uniform smooth surface. The traditional laboratory methods measure only a few samples from the entire tambour and there are other obvious limitations to this approach. Online measurements may be of significant value to improve the surface quality throughout the production. Roughness is one of the topography components and the majority of techniques measure paper by means of a single predictor of average roughness, R _a which is inadequate in providing a comprehensive characterization of the surface. Measurements, in a wide range ofwavelengths, can characterize topography components such as roughness, waviness, cockling, etc. Online measurements were taken for various grades of 8 paper reels, containing the wireside and topsides for newspaper, and uncoated and coated sides of paperboards. Their surfacecharacterization, in the spatial wavelength spectrum, from 0.1 to 10 mm was obtained. This article presents the online characterizationresults which have efficiently distinguished the surfaces of same family materials including the edge and the middle position reels of fine coatedpaperboard. Online measurements were taken, at Iggesund Paperboard Pilot Coater in Sweden, by using a recently developed OnlineTopography (OnTop) device which is based on the principle of light triangulation. © 2012 Elsevier B.V. All rights reserved.

Paper and paperboard surface quality is constantly being improved by the industry. This improvement work deals with the essential fact that the surface topography must be measured, both in relation to offline and online measurements for the manufactured products. Most measurements relating to surface topography (especially online) are performed either in the machine direction (MD) or in the cross direction (CD). It has been the opinion of SCA Ortviken AB and Iggesund Paperboard AB that the surface topography amplitudes are almost always higher in the CD than in the MD, for their products which consist of newspaper and paperboard. This article aims to investigate the rela-tionship between the CD and the MD surface topography amplitudes for a wide range of spatial wavelength for both newspaper and paperboard. The tests and investiga-tions have been conducted using an FRT Microprof profilometer within the range 20 μm up to 8 mm, and the results confirm that the surface topography amplitudes are higher in the CD for most of the shorter spatial wavelength within this range. The results also show significant differences between measurements for different paper qualities, suggesting a requirement to investigate the relationship between the CD and the MD topography for all paper and paperboard qualities of interest for a paper or paperboard mill, before a decision is made in relation to a measurement method.

Through Darcy’s permeability coefficient, K, one can evaluate the resistance of a flexographic ink film to the solvent penetration of an inkjet ink through a paper substrate. This resistance plays an important role for the print quality in hybrid printing applications where flexography and inkjet printing are combined. If this resistance is too high, K→0, the inkjet ink’s solvent would not penetrate into the substrate and ink smearing would occur resulting in poor printability.

Paper substrates were printed in a flexographic laboratory printing press. The flexographic printing dot area was varied to evaluate the influence of the full tone and halftone areas on K. These print outs were employed as filters for pigmented inkjet water based inks in a filtration setup. The inks had different pigment’s mean particle size which allowed us to address the influence of this parameter on the filter cake build up and consequently, its impact on K. The dot area had indeed an impact in the ink’s solvent penetration as we observed that the higher the dot area, the lower the K value, meaning that the resistance for ink´s solvent flow was higher. The pigment’s mean particle size also showed influence on K, as we observed that the bigger the pigment particles, the higher the K.

 The substrates were selected after a screening based on inkjet ink absorption speed evaluated through a print rub off test and line width measurements of printed lines.

We also printed the pre-printed flexography images using a KM 512 piezoelectric printing head and one of the inks used during filtration to evaluate the inkjet printing quality for this hybrid printing approach. We observed wider, less blurry and ragged lines with increased dot area. No ink smearing was observed for the print outs.

The goals for most of today´s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with �state-of-the-art� components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system�s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvements to achieve even higher performance.

All who is involved in electronic design knows that one of the critical issues

in today’s electronic is the power consumption. Designers are always looking for

new approaches in order to reduce currents while still retain performance.

Floating-gate (FGMOS) circuits have previously been shown to be a promising

technique to improve speed and still keep the power consumption low when

power supply is reduced below subthreshold voltage for the transistors.

In this thesis, the goal is to determine how good floating-gate circuits can be

compared to conventional static CMOS when the circuits are working in

subthreshold. The most interesting performance parameters are speed and power

consumption and specifically the Energy-Delay Product (EDP) that is a

combination of those two. To get a view over how the performance varies and how

good the FGMOS circuits are at their best case, the circuits have been designed and

simulated for best case performance.

The investigation also includes trade-offs with speed and power

consumption for better performance, how to select floating-gate capacitances, how

a large circuit fan-in will affect performance and also the influence of different

kinds of refresh circuits.

The first simulations of the FGMOS circuits in a 0.13 μm process have

several interesting results. First of all, in the best case it is shown that FGMOS has

potential to achieve up to 260 times in better EDP-performance compared to CMOS

at 150 mV power supply. Continuing with simulations of FGMOS capacitances

shows that minimum floating-gate capacitance can be as small as 400 fF and more

realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

capacitances included). Other aspects of FGMOS design have been to look at how

refresh circuits will affect performance (semi-floating-gate circuits) and how a

larger fan-in will change noise margin and EDP. It turns out that refresh circuits

with the same transistor size does not give a noticeable change in performance

while an increase of 8 times in size will give between 5 and 10 times wors EDP.

When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

150 mV.

Finally, it should be kept in mind that tuning the performance of FGMOS

circuits with trade-offs and by changing the floating-gate voltages to achieve

results like the ones stated above will also always affect the noise margins, NM, of

the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

fabricated circuit with that NM may not be as functional as simulations suggests.

The probability to design functional FGMOS circuits in subthreshold does not

seem to be a problem though.

When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.

The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.

For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

Many companies face the fact that the work must be adapted to the globalization so competitiveness can be maintained. One way to do it is to work geographically distributed and reach competence personnel and more customers while 24/7-work becomes possible. But to effectively work distributed over space and time, a consciousness about the limitations that this entails and how to overcome them are necessary. Sandvik IT is facing changes and the trend is toward more geographically distributed teams. The purpose of this study was therefore focused on the key factors for distributed work and how Kanban can contribute to effective distributed work. How Sandvik IT's supporting group, Service Development Office (SDO) should support the distributed work has also been evaluated. The basic theory is a compilation of literary works such as books and above all scientific articles. From the theory four key areas of distributed work was identified; working methods and coordination, communication, leadership and team spirit. A fifth point was also added, which was about the teamstart. Based on these five areas the interview - and survey questions was formed. SDO selected three teams with informants, and the team leaders/coordinators were interviewed and other staff received the survey. The results were then compared with the initial theory and via analysis 16 key factors for distributed work (at Sandvik IT) could be found. E.g. leader's consciousness, a well-established work method, shared knowledge and social interaction. The factors were also categorized into: Set-up, teams start and finally maintenance and development. To a large extent the key factors and the needs could be met by Kanban, but the recommendation is that SDO complements with (in particular) an education for team leaders/coordinators. It came to be seen as a prerequisite for the distributed work. The survey's response rate and the interviews outcome were good and the result was coherent. Hence the report can be seen as a report with high validity and reliability in an inter-organizational view.

AIM: Children and adolescents in the industrial world are becoming less

physically active and are adopting a sedentary lifestyle in front of computers

and TV. The aim of the present investigation was to determine self-related

health, physical activity, prevalence of overweight and body complaints in

high school students in Norway, and to compare students in academic

programs with those in vocational programs. METHODS: Seven hundred and

two high school students aged 16-19 years were included in the study. A

questionnaire was completed in three high schools and included questions

about weight and height, health, physical activity, type of physical

activity/sport, intensity, possible injuries or complaints during the last three

months. RESULTS: Twenty three percent of the students suffers from

overweight/obesity are at risk of being overweight. Males reported better

health than females (P<0.02). Sixty-six percent of the study group reported

body complaints during the last three months, a higher number of females

than males (P=0.001). Students in vocational programs reported poorer selfrelated

health than those in academic programs and the males reported

better self-related health generally than females. Furthermore, there were a

higher level of prevalence of overweight students in vocational programs

than academic programs (P=0.039). CONCLUSION: It is important to make it

easy for school children and adolescents to do physical activity at school and

during leisure time in order to prevent overweight and obesity as well as

chronic diseases later in life.

The aim of this investigation was to study self-related health, physical activity and level of exertion, as well as body complaints in Swedish high school students. A total of 993 high school students aged 16–19 years participated in the study. A questionnaire was completed at school and included questions about self-related health, physical activity behavior, type of physical activity/sport, intensity, duration, possible injuries or complaints, and absence from physical training at school, during the last 3 months. The results showed that 26% of the high school students participated in sports on a regular basis. Males reported significantly better health than females (p < 0.0005). A significantly higher number of females participated in physical activities at a lower level of effort (p < 0.0005) and a higher number of males trained at a higher level of effort (p < 0.005). Sixty-one percent reported body pain during the last 3 months, representing a higher number of females than males (p = 0.03). A higher number of females than males reported complaints from the back (p = 0.002), the knees (p = 0.015), the neck (p = 0.001), and the hip (p = 0.015). Females with body complaints reported poorer health than those without complaints. There was a correlation between poor self-related health and a lower level of physical effort (0.219; p < 0.001). The results showed that the prevalence of musculoskeletal symptoms was high in this population and demonstrated a certain association with self-related health. Therefore, it is important to make it easy for adolescents to perform physical activity at school and during their leisure time in order to prevent chronic diseases.