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  • 1.
    Abdalla, Munir A
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A CMOS APS for dental X-ray imaging using scintillating sensors2001In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, E-ISSN 1872-9576, Vol. 460, no 1, p. 197-203Article in journal (Refereed)
    Abstract [en]

    In this paper we present an integrating CMOS Active Pixel Sensor (APS) circuit to be used with scintillator type X-ray sensors for intra oral dental X-ray imaging systems. Different pixel architectures were constructed to explore their performance characteristics and to study the feasibility of the development of such systems using the CMOS technology. A prototype 64×80 pixel array has been implemented in a CMOS 0.8 μm double poly n-well process with a pixel pitch of 50 μm. A spectral sensitivity measurement for the different pixels topologies, as well as measured X-ray direct absorption in the different APSs are presented. A measurement of the output signal showed a good linearity over a wide dynamic range. This chip showed that the very low sensitivity of the CMOS APSs to direct X-ray exposure adds a great advantage to the various CMOS advantages over CCD-based imaging systems.

  • 2.
    Abdalla, Munir A
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A new biasing method for CMOS preamplifier-shapers2000In: ICECS 2000: 7TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS & SYSTEMS, VOLS I AND II, 2000, p. 15-18Conference paper (Refereed)
  • 3.
    Abdalla, Munir A
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    An integrating CMOS APS for X-ray imaging with an in-pixel preamplifier2001In: Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, ISSN 0168-9002, E-ISSN 1872-9576, Vol. 466, no 1, p. 232-236Article in journal (Refereed)
    Abstract [en]

    We present in this paper an integrating CMOS Active Pixel Sensor (APS) circuit coated with scintillator type sensors for intra-oral dental X-ray imaging systems. The photosensing element in the pixel is formed by the p-diffusion on the n-well diode. The advantage of this photosensor is its very low direct absorption of X-rays compared to the other available photosensing elements in the CMOS pixel. The pixel features an integrating capacitor in the feedback loop of a preamplifier of a finite gain in order to increase the optical sensitivity. To verify the effectiveness of this in-pixel preamplification, a prototype 32 x 80 element CMOS active pixel array was implemented in a 0.8 mum CMOS double poly, n-well process with a pixel pitch of 50 mum. Measured results confirmed the improved optical sensitivity performance of the APS. Various measurements on device performance are presented.

  • 4.
    Abdalla, Munir
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Dubaric, Ervin
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Nilsson, Hans-Erik
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    A scintillator-coated phototransistor pixel sensor with dark current cancellation2001In: cecs2001: 8th IEEE international conference on electronics, circuits and systems, Vols. I-III, Conference Proceedings, 2001, p. 663-667Conference paper (Other academic)
  • 5.
    Abdalla, Suliman A
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Architecture and circuit design of photon counting readout for X-ray imaging sensors2007Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    Hybrid pixel array detectors for X-ray imaging are based on different technologies for sensor and readout electronics. The readout electronics are based on standard CMOS technologies that are experiencing continuously rapid improvements by means of down-scaling the feature sizes, which in turn lead to higher transistor densities, lower power consumption, and faster circuits. For pixel-array imaging sensors the improvements in CMOS technology opens up new possibilities of integrating more functionality in the pixels for local processing of the sensor data. However, new issues related to the tight integration of both analog and digital processing circuits within the small area of a pixel must also be evaluated.

    The advantages of down-scaling the CMOS technology can be utilized to increase the spatial resolution by reducing the pixel sizes. Recent research indicates however that the bottleneck in reaching further spatial resolution in X-ray imaging sensors may not be limited by the circuit area occupied by the functions necessary in the pixels, but are instead related to problems associated with charge-sharing of charges generated by the sensor which are distributed over a neighbourhood of pixels and will limit the spatial resolution and lead to a distortion of the energy spectrum. In this thesis a mechanism to be implemented in the readout circuits is proposed in order to suppress the charge-sharing effects. The proposed architecture and its circuit implementation are evaluated with respect to circuit complexity (area) and power consumption. For a photon-counting pixel it is demonstrated that the complete pixel, with charge-sharing suppression mechanism, can be implemented using 300 transistors with an idle power consumption of 2.7μW in a 120nm CMOS technology operating with a 1.2V power supply.

    The improvements in CMOS technology can also be used for increasing the range of applications for X-ray imaging sensors. In this thesis, an architecture is proposed for multiple energy discrimination, called color X-ray imaging. The proposed solution is the result of balancing the circuit complexity and the image quality. The method is based on color sub-sampling with intensity biasing. For three-level energy discrimination, that corresponds to color imaging systems for visible light with R, G, and B color components, the increase in circuit complexity will be only 20% higher than that for the Bayer method but results in significantly better image quality.

    As the circuit complexity in the digital processing within each pixel is increased, the digitally induced noise may play an increasingly important role for the signal-to-noise ratio in the measurements. In this thesis an initial study is conducted regarding how the digital switching noise affects the analog amplifiers in the photon-counting pixel.

  • 6.
    Abdalla, Suliman
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Nilsson, Hans-Erik
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Circuit Implementation of Mechanism for Charge-Sharing Suppression for Photon-Counting Pixel Arrays2005In: 23rd NORCHIP Conference 2005, IEEE conference proceedings, 2005, p. 137-140, article id 1597008Conference paper (Refereed)
    Abstract [en]

    This work proposes an efficient circuit implementation of a mechanism for charge-sharing suppression in photon-counting pixel arrays based on current-mode circuits for the analog parts. The additional circuits needed for charge-sharing suppression in a four-pixel cluster, leads to an increase in power consumption of 36% and only a marginal increase in circuit area. The implemented pixel with window-discrimination, managing charge-sharing in a four-pixel cluster and with an event-counter of 13 bits, consists of 300 transistors and has a power consumption of 2.7 μW when idle. It is implemented in a 120nm CMOS process and the presented results are based on simulations.

  • 7.
    Abdalla, Suliman
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thim [Lundgren], Jan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Architecture and Circuit Design for Color X-Ray Pixal Array Detector Read-Out Electronics2007In: 24th Norchip Conference, 2006, New York: IEEE conference proceedings, 2007, p. 271-276, article id 4126997Conference paper (Refereed)
    Abstract [en]

    This paper proposes an area- and power-efficient implementation of the read-out electronics for color X-ray pixel detectors for imaging. Introducing multiple levels of energy discrimination will increase the complexity of the read-out electronics in each pixel. The proposed architecture has full resolution for the intensity and reduced resolution for the energy spectrum (color), which leads to a good compromise of image quality and circuit complexity. We show that the increase in complexity, compared to single energy-range pixel, will lead to increase in circuit area of less than 20%.

  • 8.
    Abdul Waheed, Malik
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thörnberg, Benny
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Cheng, Xin
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Kjeldsberg, Per Gunnar
    NTNU.
    Generalized Architecture for a Real-time Computation of an Image Component Features on a FPGAManuscript (preprint) (Other academic)
    Abstract [en]

    This paper describes a generalized architecture for real-time component labeling and computation of image component features. Computing real-time image component features is one of the most important paradigms for modern machine vision systems. Embedded machine vision systems demand robust performance, power efficiency as well as minimum area utilization. The presented architecture can easily be extended with additional modules for parallel computation of arbitrary image component features. Hardware modules for component labeling and feature calculation run in parallel. This modularization makes the architecture suitable for design automation. Our architecture is capable of processing 390 video frames per second of size 640x480 pixels. Dynamic power consumption is 24.20mW at 86 frames per second on a Xilinx Spartran6 FPGA.

  • 9. Aboelfotoh, M O
    et al.
    Fröjdh, Christer
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Petersson, Sture
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Schottky-barrier behavior of metals on n- and p-type 6H-SiC2003In: Physical Review B Condensed Matter, ISSN 0163-1829, E-ISSN 1095-3795, Vol. 67, no 7, p. 075312-Article in journal (Refereed)
  • 10.
    Ahmad, Jawad
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Andersson, Henrik
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Sidén, Johan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Sitting Posture Recognition using Screen Printed Large Area Pressure Sensors2017In: Proceedings of IEEE Sensors, IEEE, 2017, p. 232-234Conference paper (Refereed)
    Abstract [en]

    In the biomedical sector, pressure sensors exhibit an important role towards monitoring and recognition of sitting posture for wheelchair users, which is helpful for pressure ulcer prevention and cure.  In this paper, a flexible and inexpensive screen printed large area pressure sensing system is presented. The large area sensor comprise three layers, is able to cancel-out false pressure detection, and achieves a sitting classification accuracy over 80 percent. The sensor matrix contains 16 sensors distributed over an area of 23.5 cm × 21.5 cm and the pressure points are monitored at a scanning rate of 77 Hz. The sensor system provides wireless communication and a Windows based GUI is developed that allows real-time presentation of pressure data by means of a pressure map. The presented sensor design targets smart wheelchairs but is suitable for any low cost and high throughput pressure distribution monitoring systems. 

  • 11.
    Ahmad, Naeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Modelling and optimization of sky surveillance visual sensor network2012Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    A Visual Sensor Network (VSN) is a distributed system of a largenumber of camera sensor nodes. The main components of a camera sensornode are image sensor, embedded processor, wireless transceiver and energysupply. The major difference between a VSN and an ordinary sensor networkis that a VSN generates two dimensional data in the form of an image, whichcan be exploited in many useful applications. Some of the potentialapplication examples of VSNs include environment monitoring, surveillance,structural monitoring, traffic monitoring, and industrial automation.However, the VSNs also raise new challenges. They generate large amount ofdata which require higher processing powers, large bandwidth requirementsand more energy resources but the main constraint is that the VSN nodes arelimited in these resources.This research focuses on the development of a VSN model to track thelarge birds such as Golden Eagle in the sky. The model explores a number ofcamera sensors along with optics such as lens of suitable focal length whichensures a minimum required resolution of a bird, flying at the highestaltitude. The combination of a camera sensor and a lens formulate amonitoring node. The camera node model is used to optimize the placementof the nodes for full coverage of a given area above a required lower altitude.The model also presents the solution to minimize the cost (number of sensornodes) to fully cover a given area between the two required extremes, higherand lower altitudes, in terms of camera sensor, lens focal length, camera nodeplacement and actual number of nodes for sky surveillance.The area covered by a VSN can be increased by increasing the highermonitoring altitude and/or decreasing the lower monitoring altitude.However, it also increases the cost of the VSN. The desirable objective is toincrease the covered area but decrease the cost. This objective is achieved byusing optimization techniques to design a heterogeneous VSN. The core ideais to divide a given monitoring range of altitudes into a number of sub-rangesof altitudes. The sub-ranges of monitoring altitudes are covered by individualsub VSNs, the VSN1 covers the lower sub-range of altitudes, the VSN2 coversthe next higher sub-range of altitudes and so on, such that a minimum cost isused to monitor a given area.To verify the concepts, developed to design the VSN model, and theoptimization techniques to decrease the VSN cost, the measurements areperformed with actual cameras and optics. The laptop machines are used withthe camera nodes as data storage and analysis platforms. The area coverage ismeasured at the desired lower altitude limits of homogeneous as well asheterogeneous VSNs and verified for 100% coverage. Similarly, the minimumresolution is measured at the desired higher altitude limits of homogeneous aswell as heterogeneous VSNs to ensure that the models are able to track thebird at these highest altitudes.

  • 12.
    Ahmad, Naeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Modelling, optimization and design of visual sensor networks for sky surveillance2013Doctoral thesis, comprehensive summary (Other academic)
  • 13.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Model, placement optimization and verification of a sky surveillance visual sensor network2013In: International Journal of Space-Based and Situated Computing (IJSSC), ISSN 2044-4893, E-ISSN 2044-4907, Vol. 3, no 3, p. 125-135Article in journal (Refereed)
    Abstract [en]

    A visual sensor network (VSN) is a distributed system of a large number of camera nodes, which generates two dimensional data. This paper presents a model of a VSN to track large birds, such as golden eagle, in the sky. The model optimises the placement of camera nodes in VSN. A camera node is modelled as a function of lens focal length and camera sensor. The VSN provides full coverage between two altitude limits. The model can be used to minimise the number of sensor nodes for any given camera sensor, by exploring the focal lengths that fulfils both the full coverage and minimum object size requirement. For the case of large bird surveillance, 100% coverage is achieved for relevant altitudes using 20 camera nodes per km² for the investigated camera sensors. A real VSN is designed and measurements of VSN parameters are performed. The results obtained verify the VSN model.

  • 14.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Cost Optimization of a Sky Surveillance Visual Sensor Network2012In: Proceedings of SPIE - The International Society for Optical Engineering, Belgium: SPIE - International Society for Optical Engineering, 2012, p. Art. no. 84370U-Conference paper (Refereed)
    Abstract [en]

    A Visual Sensor Network (VSN) is a network of spatially distributed cameras. The primary difference between VSN and other type of sensor network is the nature and volume of information. A VSN generally consists of cameras, communication, storage and central computer, where image data from multiple cameras is processed and fused. In this paper, we use optimization techniques to reduce the cost as derived by a model of a VSN to track large birds, such as Golden Eagle, in the sky. The core idea is to divide a given monitoring range of altitudes into a number of sub-ranges of altitudes. The sub-ranges of altitudes are monitored by individual VSNs, VSN1 monitors lower range, VSN2 monitors next higher and so on, such that a minimum cost is used to monitor a given area. The VSNs may use similar or different types of cameras but different optical components, thus, forming a heterogeneous network.  We have calculated the cost required to cover a given area by considering an altitudes range as single element and also by dividing it into sub-ranges. To cover a given area with given altitudes range, with a single VSN requires 694 camera nodes in comparison to dividing this range into sub-ranges of altitudes, which requires only 96 nodes, which is 86% reduction in the cost.

  • 15.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Modeling and Verification of a Heterogeneous Sky Surveillance Visual Sensor Network2013In: International Journal of Distributed Sensor Networks, ISSN 1550-1329, E-ISSN 1550-1477, p. Art. id. 490489-Article in journal (Refereed)
    Abstract [en]

    A visual sensor network (VSN) is a distributed system of a large number of camera nodes and has useful applications in many areas. The primary difference between a VSN and an ordinary scalar sensor network is the nature and volume of the information. In contrast to scalar sensor networks, a VSN generates two-dimensional data in the form of images. In this paper, we design a heterogeneous VSN to reduce the implementation cost required for the surveillance of a given area between two altitude limits. The VSN is designed by combining three sub-VSNs, which results in a heterogeneous VSN. Measurements are performed to verify full coverage and minimum achieved object image resolution at the lower and higher altitudes, respectively, for each sub-VSN. Verification of the sub-VSNs also verifies the full coverage of the heterogeneous VSN, between the given altitudes limits. Results show that the heterogeneous VSN is very effective to decrease the implementation cost required for the coverage of a given area. More than 70% decrease in cost is achieved by using a heterogeneous VSN to cover a given area, in comparison to homogeneous VSN. © 2013 Naeem Ahmad et al.

  • 16.
    Ahmad, Naeem
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Imran, Muhammad
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Khursheed, Khursheed
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Model and placement optimization of a sky surveillance visual sensor network2011In: Proceedings - 2011 International Conference on Broadband and Wireless Computing, Communication and Applications, BWCCA 2011, IEEE Computer Society, 2011, p. 357-362Conference paper (Refereed)
    Abstract [en]

    Visual Sensor Networks (VSNs) are networks which generate two dimensional data. The major difference between VSN and ordinary sensor network is the large amount of data. In VSN, a large number of camera nodes form a distributed system which can be deployed in many potential applications. In this paper we present a model of the physical parameters of a visual sensor network to track large birds, such as Golden Eagle, in the sky. The developed model is used to optimize the placement of the camera nodes in the VSN. A camera node is modeled as a function of its field of view, which is derived by the combination of the lens focal length and camera sensor. From the field of view and resolution of the sensor, a model for full coverage between two altitude limits has been developed. We show that the model can be used to minimize the number of sensor nodes for any given camera sensor, by exploring the focal lengths that both give full coverage and meet the minimum object size requirement. For the case of large bird surveillance we achieve 100% coverage for relevant altitudes using 20 camera nodes per km2 for the investigated camera sensors.

  • 17.
    Ahmad, Nisar
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Design and Implementation of a High Frequency Flyback Converter2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The power supply designers choose flyback topology due to its promising features of design simplicity, cost effectiveness and multiple outputs handling capability. The designed product based on flyback topology should be smaller in size, cost effective and energy efficient. Similarly, designers focus on reducing the circuit losses while operating at high frequencies that affect the converter efficiency and performance. Based on the above circumstances, an energy efficient open loop high frequency flyback converter is designed and operated in MHz frequency region using step down multilayer PCB planar transformer. The maximum efficiency of 84.75% is observed and maximum output power level reached is 22.8W. To overcome the switching losses, quasi-resonant soft switching technique is adopted and a high voltage CoolMOS power transistor is used.

  • 18.
    Ahmad, Shabir
    et al.
    Jeju National University, Jeju, South Korea.
    Hussain, Ishfaq
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Fayaz, Muhammad
    Jeju National University, Jeju, South Korea.
    Kim, Do-Hyeun
    Jeju National University, Jeju, South Korea.
    A Distributed Approach towards Improved Dissemination Protocol for Smooth Handover in MediaSense IoT Platform2018In: Processes, ISSN 2227-9717, E-ISSN 1099-5862, Vol. 6, no 5, article id 46Article in journal (Refereed)
    Abstract [en]

    Recently, the Internet has been utilized by many applications to convey time-sensitive messages. The persistently expanding Internet coverage and its easy accessibility have offered to ascend to a problem which was once regarded as not essential to contemplate. Nowadays, the Internet has been utilized by many applications to convey time-sensitive messages. Wireless access points have widely been used but these access points have limitations regarding area coverage. So for covering a wider space, various access points need to be introduced. Therefore, when the user moves to some other place, the devices expected to switch between access points. Packet loss amid the handovers is a trivial issue. MediaSense is an Internet of Things distributed architecture enabling the development of the IoT application faster. It deals with this trivial handover issue by utilizing a protocol called Distributed Context eXchange Protocol. However, this protocol is centralized in nature and also suffers in a scenario when both sender and receiver address change simultaneously. This paper presents a mechanism to deal with this scenario and presents a distributed solution to deal with this issue within the MediaSense platform. The proposed protocol improves dissemination using retransmission mechanism to diminish packet loss. The proposed protocol has been delineated with a proof of concept chat application and the outcomes have indicated a significant improvement in terms of packet loss.

  • 19.
    Ahmad, Waqas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Palmieri, Luca
    University of Padova, Italy.
    Koch, Reinhard
    Christian-Albrechts-University of Kiel, Germany.
    Sjöström, Mårten
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    The Plenoptic Dataset2018Data set
    Abstract [en]

    The dataset is captured using two different plenoptic cameras, namely Illum from Lytro (based on plenoptic 1.0 model) and R29 from Raytrix (based on plenoptic 2.0 model). The scenes selected for the dataset were captured under controlled conditions. The cameras were mounted onto a multi-camera rig that was mechanically controlled to move the cameras with millimeter precision. In this way, both cameras captured the scene from the same viewpoint.

  • 20.
    Ahmad, Waqas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Sjöström, Mårten
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Olsson, Roger
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Compression scheme for sparsely sampled light field data based on pseudo multi-view sequences2018In: SPIE Photonics Europe 2018: Proceeding, 2018Conference paper (Refereed)
    Abstract [en]

    With the advent of light field acquisition technologies, the captured information of the scene is enriched by having both angular and spatial information. The captured information provides additional capabilities in the post processing stage, e.g. refocusing, 3D scene reconstruction, synthetic aperture etc. Light field capturing devices are classified in two categories. In the first category, a single plenoptic camera is used to capture a densely sampled light field, and in second category, multiple traditional cameras are used to capture a sparsely sampled light field. In both cases, the size of captured data increases with the additional angular information. The recent call for proposal related to compression of light field data by JPEG, also called “JPEG Pleno”, reflects the need of a new and efficient light field compression solution. In this paper, we propose a compression solution for sparsely sampled light field data. In a multi-camera system, each view depicts the scene from a single perspective. We propose to interpret each single view as a frame of pseudo video sequence. In this way, complete MxN views of multi-camera system are treated as M pseudo video sequences, where each pseudo video sequence contains N frames. The central pseudo video sequence is taken as base View and first frame in all the pseudo video sequences is taken as base Picture Order Count (POC). The frame contained in base view and base POC is labeled as base frame. The remaining frames are divided into three predictor levels. Frames placed in each successive level can take prediction from previously encoded frames. However, the frames assigned with last prediction level are not used for prediction of other frames. Moreover, the rate-allocation for each frame is performed by taking into account its predictor level, its frame distance and view wise decoding distance relative to the base frame. The multi-view extension of high efficiency video coding (MV-HEVC) is used to compress the pseudo multi-view sequences. The MV-HEVC compression standard enables the frames to take prediction in both direction (horizontal and vertical d), and MV-HEVC parameters are used to implement the proposed 2D prediction and rate allocation scheme. A subset of four light field images from Stanford dataset are compressed, using the proposed compression scheme on four bitrates in order to cover the low to high bit-rates scenarios. The comparison is made with state-of-art reference encoder HEVC and its real-time implementation X265. The 17x17 grid is converted into a single pseudo sequence of 289 frames by following the order explained in JPEG Pleno call for proposal and given as input to the both reference schemes. The rate distortion analysis shows that the proposed compression scheme outperforms both reference schemes in all tested bitrate scenarios for all test images. The average BD-PSNR gain is 1.36 dB over HEVC and 2.15 dB over X265.

  • 21.
    Ahmad, Waqas
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Vagharshakyan, Suren
    Tampere University of Technology, Finland.
    Sjöström, Mårten
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Gotchev, Atanas
    Tampere University of Technology, Finland.
    Bregovic, Robert
    Tampere University of Technology, Finland.
    Olsson, Roger
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Systems and Technology.
    Shearlet Transform Based Prediction Scheme for Light Field Compression2018Conference paper (Refereed)
    Abstract [en]

    Light field acquisition technologies capture angular and spatial information ofthe scene. The spatial and angular information enables various post processingapplications, e.g. 3D scene reconstruction, refocusing, synthetic aperture etc at theexpense of an increased data size. In this paper, we present a novel prediction tool forcompression of light field data acquired with multiple camera system. The captured lightfield (LF) can be described using two plane parametrization as, L(u, v, s, t), where (u, v)represents each view image plane coordinates and (s, t) represents the coordinates of thecapturing plane. In the proposed scheme, the captured LF is uniformly decimated by afactor d in both directions (in s and t coordinates), resulting in a sparse set of views alsoreferred to as key views. The key views are converted into a pseudo video sequence andcompressed using high efficiency video coding (HEVC). The shearlet transform basedreconstruction approach, presented in [1], is used at the decoder side to predict thedecimated views with the help of the key views.Four LF images (Truck, Bunny from Stanford dataset, Set2 and Set9 from High DensityCamera Array dataset) are used in the experiments. Input LF views are converted into apseudo video sequence and compressed with HEVC to serve as anchor. Rate distortionanalysis shows the average PSNR gain of 0.98 dB over the anchor scheme. Moreover, inlow bit-rates, the compression efficiency of the proposed scheme is higher compared tothe anchor and on the other hand the performance of the anchor is better in high bit-rates.Different compression response of the proposed and anchor scheme is a consequence oftheir utilization of input information. In the high bit-rate scenario, high quality residualinformation enables the anchor to achieve efficient compression. On the contrary, theshearlet transform relies on key views to predict the decimated views withoutincorporating residual information. Hence, it has inherit reconstruction error. In the lowbit-rate scenario, the bit budget of the proposed compression scheme allows the encoderto achieve high quality for the key views. The HEVC anchor scheme distributes the samebit budget among all the input LF views that results in degradation of the overall visualquality. The sensitivity of human vision system toward compression artifacts in low-bitratecases favours the proposed compression scheme over the anchor scheme.

  • 22.
    Ahonen, Mikko
    et al.
    Institute of Environmental Health and Safety, Tallinn, Estonia.
    Koppel, Tarmo
    Tallinn University of Technology, Estonia.
    Voltage transients measurements and power line communication2016In: 2016 57th International Scientific Conference on Power and Electrical Engineering of Riga Technical University (RTUCON), IEEE, 2016, p. 1-4Conference paper (Refereed)
    Abstract [en]

    Power line communication (PLC) connects energy producers with energy consumers. In the European Union stricter guidelines are under development to limit disturbances in the 2-150 kHz frequency range, because devices utilising PLC do not work. This study measured voltage transients in 22 locations and identified sources for noise. Home environments and public buildings were measured. Measurements were conducted in the frequency range of 150 kHz-500 kHz (according to EN 55011 to EN 55022) and in the lower frequency range of 3 kHz to 95 kHz. Results indicate that voltage transients are generated mostly by switching mode power supplies, pumps, rectifiers, inverters and even low quality smart meters. Several of these devices exceeded PLC standard level, 122 dBμV. Additionally we demonstrate that basic power quality recordings do not provide enough information to mitigate PLC problems occurring within microseconds and frequency specific voltage transient measurements are needed.

  • 23.
    Alam, Anzar
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Manuilskiy, Anatoliy
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thim, Jan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lindgren, Johan
    Iggesund Paperboard AB, Iggesund, Sweden.
    Lidén, Joar
    SCA Ortviken AB, Sundsvall, Sweden.
    Online surface roughness characterization of paper and paperboard using a line of light triangulation technique2012In: Nordic Pulp & Paper Research Journal, ISSN 0283-2631, E-ISSN 2000-0669, Vol. 27, no 3, p. 662-670Article in journal (Refereed)
    Abstract [en]

    Within both the paper and paperboard industries, real time monitoring and measurement of surface roughness of a paper moving at high velocities is an important and challenging area of research. The uniform surface, for an entire production, can be effectively achieved by monitoring and controlling the paper surface roughness, in real time during the manufacturing steps. Presently the majority of paper industries rely on traditional laboratory profilometers. The obvious limitations of lab profilometers are that these are slow, do not measure the quality of entire reels but rather deal with only a few small pieces of samples taken from the end of the reels and it is difficult to make any possible correction in the productionlines without knowing the online roughness data. To eradicate the disadvantages associated with conventional measurements, an online prototype instrument has been developed that measures the surface roughness during the manufacturing steps, and is based on a line of lighttriangulation technique. The prototype technique will be of assistance in ensuring tight process control in order to maintain both a better and auniform quality throughout the entire production. It measures the whole reel, meter by meter, in traditional units of roughness and is also capable of characterizing the topography in a wide range of wavelength spectra. The article presents the online analyses results obtained from the developed prototype. The real time measurements, in a paperboard pilot mill, have successfully characterized and distinguished 16 different grades of newspaper and paperboard reels including reels which have the same family of quality grades and materials.

  • 24.
    Alam, Anzar
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thim, Jan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Manuilskiy, Anatoliy
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lindgren, Johan
    Iggesund Paperboard AB, Iggesund, Sweden.
    Lidén, Joar
    SCA Ortviken AB, Sundsvall, Sweden.
    Online surface characterization of paper and paperboards in a wide-range of the spatial wavelength spectrum2012In: Applied Surface Science, ISSN 0169-4332, E-ISSN 1873-5584, Vol. 258, no 20, p. 7928-7935Article in journal (Refereed)
    Abstract [en]

    In the paper industry, surface topography is the essence of both paper and paperboard, and accurate topographical measurements are equally essential in order to achieve a uniform smooth surface. The traditional laboratory methods measure only a few samples from the entire tambour and there are other obvious limitations to this approach. Online measurements may be of significant value to improve the surface quality throughout the production. Roughness is one of the topography components and the majority of techniques measure paper by means of a single predictor of average roughness, R a which is inadequate in providing a comprehensive characterization of the surface. Measurements, in a wide range ofwavelengths, can characterize topography components such as roughness, waviness, cockling, etc. Online measurements were taken for various grades of 8 paper reels, containing the wireside and topsides for newspaper, and uncoated and coated sides of paperboards. Their surfacecharacterization, in the spatial wavelength spectrum, from 0.1 to 10 mm was obtained. This article presents the online characterizationresults which have efficiently distinguished the surfaces of same family materials including the edge and the middle position reels of fine coatedpaperboard. Online measurements were taken, at Iggesund Paperboard Pilot Coater in Sweden, by using a recently developed OnlineTopography (OnTop) device which is based on the principle of light triangulation. © 2012 Elsevier B.V. All rights reserved.

  • 25.
    Alam, Mohammad Anzar
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Thim, Jan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Manuilskiy, Anatoliy
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Westerlind, Christina
    SCA R&D Centre, Sundsvall, Sweden.
    Lindgren, Johan
    Iggesund Paperboard AB, Iggesund, Sweden.
    Lidén, Joar
    SCA Ortviken AB, Sundsvall, Sweden.
    Investigation of the surface topographical differences between the Cross Direction and the Machine Direction for newspaper and paperboard2011In: Nordic Pulp & Paper Research Journal, ISSN 0283-2631, E-ISSN 2000-0669, Vol. 26, no 4, p. 468-475Article in journal (Refereed)
    Abstract [en]

    Paper and paperboard surface quality is constantly being improved by the industry. This improvement work deals with the essential fact that the surface topography must be measured, both in relation to offline and online measurements for the manufactured products. Most measurements relating to surface topography (especially online) are performed either in the machine direction (MD) or in the cross direction (CD). It has been the opinion of SCA Ortviken AB and Iggesund Paperboard AB that the surface topography amplitudes are almost always higher in the CD than in the MD, for their products which consist of newspaper and paperboard. This article aims to investigate the rela-tionship between the CD and the MD surface topography amplitudes for a wide range of spatial wavelength for both newspaper and paperboard. The tests and investiga-tions have been conducted using an FRT Microprof profilometer within the range 20 μm up to 8 mm, and the results confirm that the surface topography amplitudes are higher in the CD for most of the shorter spatial wavelength within this range. The results also show significant differences between measurements for different paper qualities, suggesting a requirement to investigate the relationship between the CD and the MD topography for all paper and paperboard qualities of interest for a paper or paperboard mill, before a decision is made in relation to a measurement method.

  • 26. Alastalo, Ari
    et al.
    Mattila, Tomi
    Leppäniemi, Jakkoo
    Suhonen, Mika
    Kololuomo, Terho
    Schaller, Andreas
    Andersson, Henrik
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Manuilskiy, Anatoliy
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Gao, Jinlan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Nilsson, Hans-Erik
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Rusu, Alexandru
    Ayöz, Suat
    Stolichnov, Igor
    Siitonen, Simo
    Gulliksson, Mikael
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Siden, Johan
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Lehnert, Tobias
    Adam, Jens
    Veith, Michael
    Merkulov, Alexey
    Damaschek, Yvonne
    Steiger, Jurgen
    Cederberg, Markus
    Konecny, Miroslav
    Printable WORM and FRAM memories and their applications2010In: Large area, organic & printed electronics (LOPE-C) 2010, 2010, p. 8-12Conference paper (Refereed)
  • 27.
    Alfredsson, Jon
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Design of a Parallel A/D-converter System on PCB - For High-Speed Sampling and Timing Error Correction: Examensarbete - Linköpings universitet2002Other (Other academic)
    Abstract [en]

    The goals for most of today´s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with �state-of-the-art� components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system�s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvements to achieve even higher performance.

  • 28.
    Alfredsson, Jon
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies2008Doctoral thesis, comprehensive summary (Other scientific)
  • 29.
    Alfredsson, Jon
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages2007Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    All who is involved in electronic design knows that one of the critical issues

    in today’s electronic is the power consumption. Designers are always looking for

    new approaches in order to reduce currents while still retain performance.

    Floating-gate (FGMOS) circuits have previously been shown to be a promising

    technique to improve speed and still keep the power consumption low when

    power supply is reduced below subthreshold voltage for the transistors.

    In this thesis, the goal is to determine how good floating-gate circuits can be

    compared to conventional static CMOS when the circuits are working in

    subthreshold. The most interesting performance parameters are speed and power

    consumption and specifically the Energy-Delay Product (EDP) that is a

    combination of those two. To get a view over how the performance varies and how

    good the FGMOS circuits are at their best case, the circuits have been designed and

    simulated for best case performance.

    The investigation also includes trade-offs with speed and power

    consumption for better performance, how to select floating-gate capacitances, how

    a large circuit fan-in will affect performance and also the influence of different

    kinds of refresh circuits.

    The first simulations of the FGMOS circuits in a 0.13 μm process have

    several interesting results. First of all, in the best case it is shown that FGMOS has

    potential to achieve up to 260 times in better EDP-performance compared to CMOS

    at 150 mV power supply. Continuing with simulations of FGMOS capacitances

    shows that minimum floating-gate capacitance can be as small as 400 fF and more

    realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

    capacitances included). Other aspects of FGMOS design have been to look at how

    refresh circuits will affect performance (semi-floating-gate circuits) and how a

    larger fan-in will change noise margin and EDP. It turns out that refresh circuits

    with the same transistor size does not give a noticeable change in performance

    while an increase of 8 times in size will give between 5 and 10 times wors EDP.

    When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

    possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

    150 mV.

    Finally, it should be kept in mind that tuning the performance of FGMOS

    circuits with trade-offs and by changing the floating-gate voltages to achieve

    results like the ones stated above will also always affect the noise margins, NM, of

    the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

    fabricated circuit with that NM may not be as functional as simulations suggests.

    The probability to design functional FGMOS circuits in subthreshold does not

    seem to be a problem though.

  • 30.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements2007In: 2007 NORCHIP, IEEE conference proceedings, 2007, p. 146-149Conference paper (Refereed)
    Abstract [en]

    When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

  • 31.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply2007In: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Berlin: Springer, 2007, p. 536-546Conference paper (Refereed)
    Abstract [en]

    To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

  • 32.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Pseudo floating-gate design limitations in Nano-CMOS with low power supply2008In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008, 2008Conference paper (Refereed)
    Abstract [en]

    This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.

     

  • 33.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations2008In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008, 2008Conference paper (Refereed)
    Abstract [en]

    The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.

     

  • 34.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold2005In: Proceedings of IFIP VLSI-SOC 2005: International Conference on Very Large Scale Integration, Edith Cowan Univ , 2005, p. 229-232Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

  • 35.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Aunet, Snorre
    Department of Informatics, University of Oslo.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure2007In: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, IEEE conference proceedings, 2007, p. 314-317Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

  • 36.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold2006In: Proceedings - IEEE International Symposium on Circuits and Systems, IEEE conference proceedings, 2006, p. 4341-4344, article id 1693590Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

  • 37.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs2006In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 1296-1299Conference paper (Refereed)
    Abstract [en]

    For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

  • 38.
    Alfredsson, Jon
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Oelmann, Bengt
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Trading Speed and Power for Reduced Substrate Noise from Digital CMOS Circuits2004In: Proceedings of IEEE International Conference on Signals and Electronic Systems, Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering , 2004Conference paper (Refereed)
  • 39.
    Ali, Majid
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information and Communication systems.
    Improving the Adaptive Context Views and Evaluate Real-Time Performance2013Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The versatility and dimension of smart phone applications is   increasing at magnificent rate and getting more and more advanced in a level that could solve complicated real time tasks. One of the important factors for such advancement has been the powerful sensors embedded on a Smartphone devices and sensory networks. Moreover, Context and Context-awareness would have remained a myth without the advent of sensors. The objective of this thesis has been to contribute to the research work carried out under the MediaSense project. Accordingly, the ultimate purpose of the thesis has been to evaluate and study the feasibility of the adaptive context view proposed in MediaSense Platform. In precise words, the thesis has done three core tasks. Firstly, the theoretical presentation of related works and the significance of the research question have been discussed through various social applications. Secondly, a proof-of-concept application has been developed to simulate what has been proposed in the research work. Finally, Android application has been designed and implemented in order to evaluate and study the techniques presented in a practical scenario. Moreover, in the android application known as SundsvallBIGBuddies, we have used the extensions designed for the existing MediaSense platform. The impact of using Android app relaying on a continuous stream of context data has been presented using graphs and tables.  In order to study the impact we used smart phone and tablets from Samsung.

  • 40.
    Allahgholi, A.
    et al.
    DESY, D-22607 Hamburg, Germany.
    Becker, J.
    DESY, D-22607 Hamburg, Germany.
    Bianco, L.
    DESY, D-22607 Hamburg, Germany.
    Bradford, R.
    Adv Photon Source, Chicago, IL USA.
    Delfs, A.
    DESY, D-22607 Hamburg, Germany.
    Dinapoli, R.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Goettlicher, P.
    DESY, D-22607 Hamburg, Germany.
    Gronewald, M.
    Univ Bonn, D-53115 Bonn, Germany.
    Graafsma, Heinz
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. DESY, D-22607 Hamburg, Germany.
    Greiffenberg, D.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Henrich, B. H.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Hirsemann, H.
    DESY, D-22607 Hamburg, Germany.
    Jack, S.
    DESY, D-22607 Hamburg, Germany.
    Klanner, R.
    Univ Hamburg, D-22761 Hamburg, Germany.
    Klyuev, A.
    DESY, D-22607 Hamburg, Germany.
    Krueger, H.
    Univ Bonn, D-53115 Bonn, Germany.
    Lange, S.
    DESY, D-22607 Hamburg, Germany.
    Marras, A.
    DESY, D-22607 Hamburg, Germany.
    Mezza, D.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Mozzanica, A.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Perova, I.
    DESY, D-22607 Hamburg, Germany.
    Xia, Q.
    DESY, D-22607 Hamburg, Germany.
    Schmitt, B.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Schwandt, J.
    Univ Hamburg, D-22761 Hamburg, Germany.
    Sheviakov, I.
    DESY, D-22607 Hamburg, Germany.
    Shi, X.
    Paul Scherrer Inst, OFLB-006, CH-5232 Villigen, Switzerland.
    Trunk, U.
    DESY, D-22607 Hamburg, Germany.
    Zhang, J.
    DESY, D-22607 Hamburg, Germany.
    The adaptive gain integrating pixel detector2016In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 11, no 2, article id C02066Article in journal (Refereed)
    Abstract [en]

    The adaptive gain integrating pixel detector (AGIPD) is a development of a collaboration between Deustsches Elektronen-Synchrotron (DESY), the Paul-Scherrer-Institute (PSI), the University of Hamburg and the University of Bonn. The detector is designed to cope with the demanding challenges of the European XFEL. Therefore it comes along with an adaptive gain stage allowing a high dynamic range, spanning from single photon sensitivity to 10(4) x 12.4 keV photons and 352 analogue memory cells per pixel. The aim of this report is to briefly explain the concepts of the AGIPD electronics and mechanics and then present recent experiments demonstrating the functionality of its key features.

  • 41.
    Allahgholi, A.
    et al.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Becker, J.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany; Cornell University, Ithaca, NY, United States .
    Bianco, L.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Delfs, A.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Arino-Estrada, G.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Gottlicher, P.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Graafsma, Heinz
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Hirsemann, H.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Jack, S.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Klyuev, A.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Lange, S.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Marras, A.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Poehlsen, J.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Sheviakov, I.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Trunk, U.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Xia, Q.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Zhang, J.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Zimmer, M.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany.
    Dinapoli, R.
    PSI, Villigen, Switzerland.
    Greiffenberg, D.
    PSI, Villigen, Switzerland.
    Mezza, D.
    PSI, Villigen, Switzerland.
    Mozzanica, A.
    PSI, Villigen, Switzerland.
    Schmitt, B.
    PSI, Villigen, Switzerland.
    Shi, X.
    PSI, Villigen, Switzerland.
    Klanner, R.
    University of Hamburg, Germany.
    Schwandt, J.
    University of Hamburg, Germany.
    Kruger, H.
    University of Bonn, Germany.
    Rah, S.
    Pohang Accelerator Laboratory, Pohang, South Korea.
    The AGIPD 1.0 ASIC: Random access high frame rate, high dynamic range X-ray camera readout for the European XFEL2015In: 2015 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, article id 7581819Conference paper (Refereed)
    Abstract [en]

    The European XFEL is an extremely brilliant Free Electron Laser Source with a very demanding pulse structure: trains of 2700 X-Ray pulses are repeated at 10 Hz. The pulses inside the train are spaced by 220 ns and each one contains up to 1012 photons of 12.4 keV, while being ≤ 100 fs in length. AGIPD (Adaptive Gain Integrating Pixel Detector) is a hybrid 1M-pixel detector developed by DESY, PSI, and the Universities of Bonn and Hamburg to cope with these properties. Thus the readout ASIC has to provide not only single photon sensitivity and a dynamic range ≳ 104 photons/pixel in the same image but also a memory for as many images of a pulse train as possible for delayed readout prior to the next train. The AGIPD 1.0 ASIC uses a 130 nm CMOS technology and radiation tolerant techniques to withstand the radiation damage incurred by the high impinging photon flux. Each ASIC contains 64 × 64 pixels of 200μmχ200μm. The circuit of each pixel contains a charge sensitive preamplifier with threefold switchable gain, a discriminator for an adaptive gain selection, and a correlated double sampling (CDS) stage to remove reset and low-frequency noise components. The output of the CDS, as well as the dynamically selected gain is sampled in a capacitor-based analogue memory for 352 samples, which occupies about 80% of a pixels area. For readout each pixel features a charge sensitive buffer. A control circuit with a command based interface provides random access to the memory and controls the row-wise readout of the data via multiplexers to four differential analogue ports. The AGIPD 1.0 full scale ASIC has been received back from the foundry in fall of 2013. Since then it has been extensively characterised also with a sensor as a single chip and in 2 × 8-chip modules for the AGIPD 1 Mpix detector. We present the design of the AGIPD 1.0 ASIC along with supporting results, also from beam tests at PETRA III and APS, and show changes incorporated in the recently taped out AGIPD 1.1 ASIC upgrade.

  • 42.
    Allahgholi, A.
    et al.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Becker, J.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Bianco, L.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Delfs, A.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Dinapoli, R.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Arino-Estrada, G.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Goettlicher, P.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Graafsma, Heinz
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Greiffenberg, D.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Hirsemann, H.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Jack, S.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Klanner, R.
    Univ Hamburg, Mittelweg 177, D-20148 Hamburg, Germany.
    Klyuev, A.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Krueger, H.
    Univ Bonn, D-53012 Bonn, Germany.
    Lange, S.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Marras, A.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Mezza, D.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Mozzanica, A.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Poehlsen, J.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Rah, S.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Xia, Q.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Schmitt, B.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Schwandt, J.
    Univ Hamburg, Mittelweg 177, D-20148 Hamburg, Germany.
    Sheviakov, I.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Shi, X.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Smoljanin, S.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Trunk, U.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Zhang, J.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Zimmer, M.
    Deutsch Elekt Synchrotron DESY, Notkestr 85, D-22607 Hamburg, Germany.
    Front end ASIC for AGIPD, a high dynamic range fast detector for the European XFEL2016In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 11, no 1, article id C01057Article in journal (Refereed)
    Abstract [en]

    The Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector for the European-XFEL. One of the detector's important parts is the radiation tolerant front end ASIC fulfilling the European-XFEL requirements: high dynamic range-from sensitivity to single 12.5keV-photons up to 104 photons. It is implemented using the dynamic gain switching technique with three possible gains of the charge sensitive preamplifier. Each pixel can store up to 352 images in memory operated in random-access mode at >= 4.5MHz frame rate. An external vetoing may be applied to overwrite unwanted frames.

  • 43.
    Allahgholi, A.
    et al.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Becker, J.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Bianco, L.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Delfs, A.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Dinapoli, R.
    Paul-Scherrer-Institut PSI, Villigen, Switzerland.
    Fretwurst, E.
    University of Bonn, Bonn, Germany.
    Göttlicher, P.
    University of Hamburg, Hamburg, Germany.
    Graafsma, Heinz
    Mid Sweden University, Faculty of Science, Technology and Media. Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Greiffenberg, D.
    Paul-Scherrer-Institut PSI, Villigen, Switzerland.
    Gronewald, M.
    University of Bonn, Bonn, Germany.
    Hirsemann, H.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Jack, S.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Klanner, R.
    University of Bonn, Bonn, Germany.
    Klyuev, A.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Krüger, H.
    University of Bonn, Bonn, Germany.
    Marras, A.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Mezza, D.
    Paul-Scherrer-Institut PSI, Villigen, Switzerland.
    Mozzanica, A.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Schmitt, B.
    Paul-Scherrer-Institut PSI, Villigen, Switzerland.
    Schwandt, J.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Sheviakov, I.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Shi, X.
    Paul-Scherrer-Institut PSI, Villigen, Switzerland.
    Xia, Q.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Zhang, J.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    Zimmer, M.
    Deutsches Elektronen-Synchrotron DESY, Hamburg, Germany.
    AGIPD, the electronics for a high speed X-ray imager at the Eu-XFEL2014In: Proceedings of Science, Proceedings of Science (PoS) , 2014, article id 253Conference paper (Refereed)
    Abstract [en]

    The AGIPD (Adaptive Gain Integrated Pixel Detector) X-ray imaging camera will be operated at the X-ray Free Electron Laser, Eu-XFEL, under construction in Hamburg, Germany. Key parameters are 1 million 200 μm square pixels, single 12.4 keV photon detection and a dynamic range to 10 000/pixel/image. The developed sensors, ASICs, PCB-electronics and FPGA firmware acquire individual images per bunch at 27 000 bunches/s, packed into 10 bunch-trains/s with a bunch separation of 222 ns. Bunch-trains are handled by 352 analogue storage cells within each pixel of the ASIC and written during the 0.6msec train delivery. Therefore AGIPD can store 3520 images/s from the delivered 27 000 bunches/s. Random addressing provides reusability of each cell after an image has been declared as low-quality, so that good images can be selected. Digitization is performed between trains (99.4 msec). In the paper all functional blocks are introduced. The details concentrate on the DAQ-chain PCB-electronics and the slow control. A dense area of 1024 ADC-channels, each with a pickup-noise filtering and sampling of up to 50 MS/s/ADC and a serial output of 700 Mbit/s/ADC. FPGAs operate the ASICs synchronized to the bunch structure and collect the bit streams from 64 ADCs/FPGA. Pre-sorted data is transmitted on 10 GbE links out of the camera head using the time between trains. The control and monitoring of the camera with 600 A current consumption is based on a micro-controller and I2C bus with an addressing architecture allowing many devices and identical modules. The high currents require planned return paths at the system level. First experimental experience with the constructed components will be presented.

  • 44.
    Allahgholi, A.
    et al.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Becker, J.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Bianco, L.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Delfs, A.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Dinapoli, R.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland..
    Goettlicher, P.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Graafsma, Heinz
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany.;Mid Sweden Univ, S-85170 Sundsvall, Sweden.
    Greiffenberg, D.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland..
    Hirsemann, H.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Jack, S.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Klanner, R.
    Univ Hamburg, D-20148 Hamburg, Germany..
    Klyuev, A.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Krueger, H.
    Univ Bonn, D-53012 Bonn, Germany..
    Lange, S.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Marras, A.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Mezza, D.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Mozzanica, A.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Rah, S.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Xia, Q.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Schmitt, B.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Schwandt, J.
    Univ Hamburg, D-20148 Hamburg, Germany.
    Sheviakov, I.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Shi, X.
    Paul Scherrer Inst, CH-5232 Villigen, Switzerland.
    Smoljanin, S.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Trunk, U.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Zhang, J.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    Zimmer, M.
    Deutsch Elektronen Synchrotron DESY, D-22607 Hamburg, Germany..
    AGIPD, a high dynamic range fast detector for the European XFEL2015In: Journal of Instrumentation, ISSN 1748-0221, E-ISSN 1748-0221, Vol. 10, no 1, article id C01023Article in journal (Refereed)
    Abstract [en]

    AGIPD-(Adaptive Gain Integrating Pixel Detector) is a hybrid pixel X-ray detector developed by a collaboration between Deutsches Elektronen-Synchrotron (DESY), Paul-Scherrer-Institut (PSI), University of Hamburg and the University of Bonn. The detector is designed to comply with the requirements of the European XFEL. The radiation tolerant Application Specific Integrated Circuit (ASIC) is designed with the following highlights: high dynamic range, spanning from single photon sensitivity up to 10(4) 12.5keV photons, achieved by the use of the dynamic gain switching technique using 3 possible gains of the charge sensitive preamplifier. In order to store the image data, the ASIC incorporates 352 analog memory cells per pixel, allowing also to store 3 voltage levels corresponding to the selected gain. It is operated in random-access mode at 4.5MHz frame rate. The data acquisition is done during the 99.4ms between the bunch trains. The AGIPD has a pixel area of 200 x 200 m m(2) and a 500 m m thick silicon sensor is used. The architecture principles were proven in different experiments and the ASIC characterization was done with a series of development prototypes. The mechanical concept was developed in the close contact with the XFEL beamline scientists and is now being manufactured. A first single module system was successfully tested at APS.

  • 45.
    Allahgholi, A.
    et al.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Becker, J.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Bianco, L.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Delfs, A.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Gottlicher, P.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Graafsma, Heinz
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Hirsemann, H.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Jack, S.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Klyuev, A.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Lange, S.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Marras, A.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Sheviakov, I.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Trunk, U.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Xia, Q.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Zhang, J.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Zimmer, M.
    Center for Free-Electron Laser Science, DESY, Hamburg, Germany .
    Dinapoli, R.
    PSI, Villigen, Switzerland .
    Greiffenberg, D.
    PSI, Villigen, Switzerland .
    Mezza, D.
    PSI, Villigen, Switzerland .
    Mozzanica, A.
    PSI, Villigen, Switzerland .
    Schmitt, B.
    PSI, Villigen, Switzerland .
    Shi, X.
    PSI, Villigen, Switzerland .
    Klanner, R.
    University of Hamburg, Germany .
    Schwandt, J.
    University of Hamburg, Germany .
    Gronewald, M.
    University of Bonn, Germany .
    Kruger, H.
    University of Bonn, Germany .
    Rah, S.
    Pohang Accelerator Laboratory, Pohang, South Korea .
    AGIPD 1.0: The high-speed high dynamic range readout ASIC for the adaptive gain integrating pixel detector at the European XFEL2016In: 2014 IEEE Nuclear Science Symposium and Medical Imaging Conference, NSS/MIC 2014, Institute of Electrical and Electronics Engineers (IEEE), 2016, article id 7431038Conference paper (Refereed)
    Abstract [en]

    AGIPD is a hybrid pixel X-ray detector developed by a collaboration between Deutsches Elektronen-Synchrotron (DESY), Paul-Scherrer-Institute (PSI), University of Hamburg and the University of Bonn. The detector is designed to comply with the requirements of the European XFEL. The radiation tolerant Application Specific Integrated Circuit (ASIC) is designed with the following highlights: high dynamic range, spanning from single photon sensitivity up to 104 × 12.4 keV photons, achieved by the use of dynamic gain switching, auto-selecting one of 3 gains of the charge sensitive pre-amplifier. To cope with the unique features of the European XFEL source, image data is stored in 352 analogue memory cells per pixel. The selected gain is stored in the same way and depth, encoded as one of 3 voltage levels. These memories are operated in random-access mode at 4.5MHz frame rate. Data is read out on a row-by-row basis via multiplexers to the DAQ system for digitisation during the 99.4ms gap between the bunch trains of the European XFEL. The AGIPD 1.0 ASIC features 64×64 pixels with a pixel area of 200×200 μm2. It is bump-bonded to a 500 μm thick silicon sensor. The principles of the chip architecture were proven in different experiments and the ASIC characterization was performed with a series of development prototypes. The mechanical concept of the detector system was developed in close contact with the XFEL beamline scientists to ensure a seamless integration into the beamline setup and is currently being manufactured. The first single module system was successfully tested at APS1 the high dynamic range allows imaging of the direct synchrotron beam along with single photon sensitivity and burst imaging of 352 subsequent frames synchronized to the source.

  • 46.
    Aloisi, Alessandro
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information and Communication systems. University of Bologna (Italy).
    Enabling communication between Wireless Sensor Networks and The Internet-of-Things: A CoAP communication stack2014Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    The thesis focuses on enabling the communication between Wireless Sensor Networks and Internet-of-Things applications.  In order to achieve this goal, the first step has been to investigate the concept of the Internet-of-Things and then to understand how this scenario could be used to interconnect multiple Wireless Sensor Networks in order to develop context-aware applications which could handle sensor data coming from this type of network. 

    The second step was to design and implement a communication stack which enabled Wireless Sensor Networks to communicate with an Internet-of-Things platform. The CoAP protocol has been used as application protocol for the communication with the Wireless Sensor Networks. The solution has been developed in Java programming language and extended the sensor and actuator layer of the Sensible Things platform. 

    The third step of this thesis has been to investigate in which real world applications the developed solution could have been used. Next a Proof of Concept application has been implemented in order to simulate a simple fire detection system, where multiple Wireless Sensor Networks collaborate to send their temperature data to a control center. The last step was to evaluate the whole system, specifically the responsiveness and the overhead introduced by the developed communication stack.

  • 47.
    Alqaysi, Hiba
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Lawal, Najeem
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Fedorov, Igor
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    O'Nils, Mattias
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    Evaluating Coverage Effectiveness of Multi-Camera Domes Placement for Volumetric Surveillance2017In: ICDSC 2017 Proceedings of the 11th International Conference on Distributed Smart Cameras, New York, NY, USA: Association for Computing Machinery (ACM), 2017, Vol. F132201, p. 49-54Conference paper (Refereed)
    Abstract [en]

    Multi-camera dome is composed of a number of cameras arranged to monitor a half sphere of the sky. Designing a network of multi-camera domes can be used to monitor flying activities in open large area, such as birds' activities in wind parks. In this paper, we present a method for evaluating the coverage effectiveness of the multi-camera domes placement in such areas. We used GPS trajectories of free flying birds over an area of 9 km2 to analyze coverage effectiveness of randomly placed domes. The analysis is based on three criteria namely, detection, positioning and the maximum resolution captured. The developed method can be used to evaluate results of designing and optimizing dome placement algorithms for volumetric monitoring systems in order to achieve maximum coverage.

  • 48.
    Ambatipudi, Radhika
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design.
    High Frequency (MHz) Planar Transformers for Next Generation Switch Mode Power Supplies2013Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Increasing the power density of power electronic converters while reducing or maintaining the same cost, offers a higher potential to meet the current trend inrelation to various power electronic applications. High power density converters can be achieved by increasing the switching frequency, due to which the bulkiest parts, such as transformer, inductors and the capacitor's size in the convertercircuit can be drastically reduced. In this regard, highly integrated planar magnetics are considered as an effective approach compared to the conventional wire wound transformers in modern switch mode power supplies (SMPS). However, as the operating frequency of the transformers increase from several hundred kHz to MHz, numerous problems arise such as skin and proximity effects due to the induced eddy currents in the windings, leakage inductance and unbalanced magnetic flux distribution. In addition to this, the core losses whichare functional dependent on frequency gets elevated as the operating frequency increases. Therefore, this thesis provides an insight towards the problems related to the high frequency magnetics and proposes a solution with regards to different aspects in relation to designing high power density, energy efficient transformers.The first part of the thesis concentrates on the investigation of high power density and highly energy efficient coreless printed circuit board (PCB) step-down transformers useful for stringent height DC-DC converter applications, where the core losses are being completely eliminated. These transformers also maintain the advantages offered by existing core based transformers such as, high coupling coefficient, sufficient input impedance, high energy efficiency and wide frequencyband width with the assistance of a resonant technique. In this regard, several coreless PCB step down transformers of different turn’s ratio for power transfer applications have been designed and evaluated. The designed multilayered coreless PCB transformers for telecom and PoE applications of 8,15 and 30W show that the volume reduction of approximately 40 - 90% is possible when compared to its existing core based counterparts while maintaining the energy efficiency of the transformers in the range of 90 - 97%. The estimation of EMI emissions from the designed transformers for the given power transfer application proves that the amount of radiated EMI from a multilayered transformer is lessthan that of the two layered transformer because of the decreased radius for thesame amount of inductance.The design guidelines for the multilayered coreless PCB step-down transformer for the given power transfer application has been proposed. The designed transformer of 10mm radius has been characterized up to the power level of 50Wand possesses a record power density of 107W/cm3 with a peak energy efficiency of 96%. In addition to this, the design guidelines of the signal transformer fordriving the high side MOSFET in double ended converter topologies have been proposed. The measured power consumption of the high side gate drive circuitvitogether with the designed signal transformer is 0.37W. Both these signal andpower transformers have been successfully implemented in a resonant converter topology in the switching frequency range of 2.4 – 2.75MHz for the maximum load power of 34.5W resulting in the peak energy efficiency of converter as 86.5%.This thesis also investigates the indirect effect of the dielectric laminate on the magnetic field intensity and current density distribution in the planar power transformers with the assistance of finite element analysis (FEA). The significanceof the high frequency dielectric laminate compared to FR-4 laminate in terms of energy efficiency of planar power transformers in MHz frequency region is also explored.The investigations were also conducted on different winding strategies such as conventional solid winding and the parallel winding strategies, which play an important role in the design and development of a high frequency transformer and suggested a better choice in the case of transformers operating in the MHz frequency region.In the second part of the thesis, a novel planar power transformer with hybrid core structure has been designed and evaluated in the MHz frequency region. The design guidelines of the energy efficient high frequency planar power transformerfor the given power transfer application have been proposed. The designed corebased planar transformer has been characterized up to the power level of 50W and possess a power density of 47W/cm3 with maximum energy efficiency of 97%. This transformer has been evaluated successfully in the resonant converter topology within the switching frequency range of 3 – 4.5MHz. The peak energy efficiency ofthe converter is reported to be 92% and the converter has been tested for the maximum power level of 45W, which is suitable for consumer applications such as laptop adapters. In addition to this, a record power density transformer has been designed with a custom made pot core and has been characterized in thefrequency range of 1 - 10MHz. The power density of this custom core transformer operating at 6.78MHz frequency is 67W/cm3 and with the peak energy efficiency of 98%.In conclusion, the research in this dissertation proposed a solution for obtaining high power density converters by designing the highly integrated, high frequency(1 - 10MHz) coreless and core based planar magnetics with energy efficiencies inthe range of 92 - 97%. This solution together with the latest semiconductor GaN/SiC switching devices provides an excellent choice to meet the requirements of the next generation ultra flat low profile switch mode power supplies (SMPS).

  • 49.
    Ambatipudi, Radhika
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Multilayered Coreless Printed Circuit Board (PCB) Step-down Transformers for High Frequency Switch Mode Power Supplies (SMPS)2011Licentiate thesis, comprehensive summary (Other academic)
    Abstract [en]

    The Power Supply Unit (PSU) plays a vital role in almost all electronic equipment. The continuous efforts applied to the improvement of semiconductor devices such as MOSFETS, diodes, controllers and MOSFET drivers have led to the increased switching speeds of power supplies. By increasing the switching frequency of the converter, the size of passive elements such as inductors, transformers and capacitors can be reduced. Hence, the high frequency transformer has become the backbone in isolated AC/DC and DC/DC converters. The main features of transformers are to provide isolation for safety purpose, multiple outputs such as in telecom applications, to build step down/step up converters and so on. The core based transformers, when operated at higher frequencies, do have limitations such as core losses which are proportional to the operating frequency. Even though the core materials are available in a few MHz frequency regions, because of the copper losses in the windings of the transformers those which are commercially available were limited from a few hundred kHz to 1MHz. The skin and proximity effects because of induced eddy currents act as major drawbacks while operating these transformers at higher frequencies. Therefore, it is necessary to mitigate these core losses, skin and proximity effects while operating the transformers at very high frequencies. This can be achieved by eliminating the magnetic cores of transformers and by introducing a proper winding structure.

    A new multi-layered coreless printed circuit board (PCB) step down transformer for power transfer applications has been designed and this maintains the advantages offered by existing core based transformers such as, high voltage gain, high coupling coefficient, sufficient input impedance and high energy efficiency with the assistance of a resonant technique. In addition, different winding structures have been studied and analysed for higher step down ratios in order to reduce copper losses in the windings and to achieve a higher coupling coefficient. The advantage of increasing the layer for the given power transfer application in terms of the coupling coefficient, resistance and energy efficiency has been reported. The maximum energy efficiency of the designed three layered transformers was found to be within the range of 90%-97% for power transfer applications operated in a few MHz frequency regions. The designed multi-layered coreless PCB transformers for given power applications of 8, 15 and 30W show that the volume reduction of approximately 40-90% is possible when compared to its existing core based counterparts. The estimation of EMI emissions from the designed transformers proves that the amount of radiated EMI from a three layered transformer is less than that of the two layered transformer because of the decreased radius for the same amount of inductance.

    Multi-layered coreless PCB gate drive transformers were designed for signal transfer applications and have successfully driven the double ended topologies such as the half bridge, the two switch flyback converter and resonant converters with low gate drive power consumption of about half a watt. The performance characteristics of these transformers have also been evaluated using the high frequency magnetic material made up of NiZn and operated in the 2-4MHz frequency region.

    These multi-layered coreless PCB power and signal transformers together with the latest semiconductor switching devices such as SiC and GaN MOSFETs and the SiC schottky diode are an excellent choice for the next generation compact SMPS.

  • 50.
    Ambatipudi, Radhika
    et al.
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Kotte, Hari Babu
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Bertilsson, Kent
    Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
    Comparison of Two Layered and Three Layered Coreless Printed Circuit Board Step-Down Power Transformers2011In: 2011 INTERNATIONAL CONFERENCE ON INSTRUMENTATION, MEASUREMENT, CIRCUITS AND SYSTEMS (ICIMCS 2011), VOL 2: FUTURE COMMUNICATION AND NETWORKING, Shenzhen: IEEE conference proceedings, 2011, p. 59-62Conference paper (Refereed)
    Abstract [en]

    In this paper the comparative results of two layered and three layered coreless Printed Circuit Board (PCB) step down 2:1 power transformers operating in MHz frequency were addressed. The  two different step down transformers approximately having same self inductances, one in two layer and the other in three layer were designed and evaluated for the given power transfer application. The performance characteristics of these transformers under similar conditions were measured and the comparative parameters of these transformers in terms of their resistances, self, leakage, mutual inductances, and coupling coefficient are analyzed. For the given output power, the measured energy efficiency of the three layered transformer is improved by 3% and the area is reduced by 32% compared to two layered transformer. The efficiency of the three layered transformer is 94.5% approximately for an output power level of 25W at an operating frequency of 2.5MHz

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