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Technology Driven Obsolescence Management for Embedded Systems
Mid Sweden University, Faculty of Science, Technology and Media, Department of Electronics Design. (STC)
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, the work presented is in relation to technology driven obsolescence management for embedded systems.

Component obsolescence problems may occur in systems with a life cycle longer than that of one or more of their components when there is a demand without enough existing stock, such as automotive, avionics, military applications, etc. This thesis analyzes the component obsolescence problem from both the design technology selection and management perspectives.

Design technologies selection is associated with hardware and software. Several hardware platforms such as COTS and field-programmable gate array (FPGA) are discussed. FPGA intellectual property (IP) portability is emphasized which will affect the obsolescence management cost. Embedded software is also a crucial part for system sustainment. A risk analysis is performed in relation to long life cycle systems for different design technologies. Different platform cases are evaluated by analyzing the essence of each case and the consequences of different risk scenarios during system maintenance. This has shown that an FPGA platform with the vendor and device independent soft IPs has the highest maintainability and the minimum redesign cost.

The reuse of a predefined IP can shorten the development times and assist the designer to meet time-to-market (TTM) requirements. System migration between devices is unavoidable, especially when it has a long life cycle expectation, so IP portability becomes an important issue for system maintenance. If an IP for FPGAs is truly portable, it must be easily adaptable to different communication interfaces, being portable between different FPGA vendors and devices, having no dependencies on the tool set and library used for the system design and no restriction on the communication interface. An M-JPEG decoder and a soft microprocessor portability analysis case study are presented in the thesis. A methodology is proposed to ease the interface modification and interface reuse, thus to increase the portability of an IP.

A strategic proactive obsolescence management model is proposed from a management perspective. This model can estimate the minimum management costs for a system with different architectures. It consists of two parts. The first is to generate a graph, which is in the form of an obsolescence management diagram. A segments table containing the data of this diagram is calculated and prepared for optimization at a second step. This second part is to find the minimum cost for system obsolescence management. Mixed integer linear programming (MILP) is used to calculate the minimum management cost and schedule. The model is open sourced thus allowing other research groups to freely download and modify it.

Both the design technology selection and the strategic proactive obsolescence management are demonstrated by an industrial display computer system case study. The results show significant cost avoidance as compared to the original method used by the company.

Finally, the research results are encapsulated into an obsolescence management cost avoidance methodology.  

Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University , 2014. , p. 178
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 186
Keywords [en]
Long life cycle, embedded system, DMSMS, obsolescnece, FPGA, IP, portability
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-21744Local ID: STCISBN: 978-91-87557-50-7 (print)OAI: oai:DiVA.org:miun-21744DiVA, id: diva2:711746
Public defence
2014-05-15, O102, Sundsvall, 11:17 (English)
Opponent
Supervisors
Funder
Knowledge FoundationAvailable from: 2014-04-17 Created: 2014-04-11 Last updated: 2017-03-06Bibliographically approved
List of papers
1. Embedded System Design with Maintenance  Consideration
Open this publication in new window or tab >>Embedded System Design with Maintenance  Consideration
2011 (English)In: Proceedings of the 34th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO, IEEE conference proceedings, 2011, p. 124-129Conference paper, Published paper (Refereed)
Abstract [en]

This paper deals with the problems of maintaining a long lifetime embedded system, including obsolescence, function change requirement or technology migration etc. The aim of the presented work is to analyze the maintainability of long lifetime embedded systems for different design technologies. FPGA platform solutions are proposed in order to ease the system maintenance. Different platform cases are evaluated by analyzing the essence of each case and the consequences of different risk scenarios during system maintenance. Finally, the conclusion is drawn that the FPGA platform with vendor and device independent soft IP is the best choice.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keywords
embedded system, maintenance, obsolescence, FPGA, soft IP
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-14308 (URN)2-s2.0-80052299852 (Scopus ID)STC (Local ID)978-1-4577-0996-8 (ISBN)STC (Archive number)STC (OAI)
Conference
34th International Convention on Information and Communication Technology, Electronics and Microelectronics, MIPRO 2011;Opatija;23 May 2011through27 May 2011;Category numberCFP1139K-CDR;Code86227
Projects
STC
Available from: 2011-08-15 Created: 2011-08-15 Last updated: 2016-10-19Bibliographically approved
2. Soft-IP Interface Modification Methodology
Open this publication in new window or tab >>Soft-IP Interface Modification Methodology
2011 (English)In: Proceedings of 2011 International Conference on Information and Electronics Engineering, 2011Conference paper, Published paper (Refereed)
Abstract [en]

The reuse of predefined Intellectual Property (IP) can lead to great success in system design and help the designer to meet time-to-market requirements. A soft IP usually needs some customization and integration efforts rather than plug-and-play. Communication interface mismatch is one of the problems that integrators often meet. This paper suggests a soft-IP interface modification methodology (SIPIMM) for systems on Field Programmable Gate Array (FPGA) SIPIMM targets an interface-based soft IP model which is introduced to ease the interface modification and interface reuse. A case study of an open-source IP is presented using SIPIMM for system integration.

Keywords
IP, FPGA, interface mismatch
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-13277 (URN)STC (Local ID)STC (Archive number)STC (OAI)
Conference
ICIEE 2011
Projects
STC
Available from: 2011-02-17 Created: 2011-02-17 Last updated: 2016-10-19Bibliographically approved
3. Portability analysis of an M-JPEG decoder IP from OpenCores
Open this publication in new window or tab >>Portability analysis of an M-JPEG decoder IP from OpenCores
2011 (English)In: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings, IEEE conference proceedings, 2011, p. 79-82Conference paper, Published paper (Refereed)
Abstract [en]

The reuse of predefined Intellectual Property (IP) can shorten development times and help the designer to meet time-to-market requirements for embedded systems. Using FPGA IP in a proper way can also mitigate the component obsolescence problem. System migration between devices is unavoidable, especially for long lifetime embedded systems, so IP portability becomes an important issue for system maintenance. This paper presents a case study analyzing the portability of an FPGA-based M-JPEG decoder IP. The lack of any clear separation between computation and communication is shown to limit the decoder's portability with respect to different communication interfaces. Technology and tool dependent firmware IP components are often supplied by FPGA vendors. It is possible for these firm IP components to reduce development time. However, the use of these technology and tool dependent firmware specifications within the M-JPEG decoder is shown to limit the decoder's portability with respect to development tools and FPGA vendors.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keywords
IP, FPGA, obsolescence, maintenance, portability, M-JPEG decoder
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-14310 (URN)10.1109/SIES.2011.5953685 (DOI)2-s2.0-80052019062 (Scopus ID)STC (Local ID)978-1-61284-819-8 (ISBN)978-1-61284-818-1 (ISBN)STC (Archive number)STC (OAI)
Conference
6th IEEE International Symposium on Industrial Embedded Systems, SIES 2011;Vasteras;15 June 2011through17 June 2011;Category numberCFP11INB-ART;Code86076
Projects
STC
Available from: 2011-08-15 Created: 2011-08-15 Last updated: 2016-10-19Bibliographically approved
4. Real-Time machine vision system using FPGA and soft-core processor
Open this publication in new window or tab >>Real-Time machine vision system using FPGA and soft-core processor
2012 (English)In: Proceedings of SPIE - The International Society for Optical Engineering, SPIE - International Society for Optical Engineering, 2012, p. Art. no. 84370Z-Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a machine vision system for real-time computation of distance and angle of a camera from reference points in the environment. Image pre-processing, component labeling and feature extraction modules were modeled at Register Transfer (RT) level and synthesized for implementation on field programmable gate arrays (FPGA). The extracted image component features were sent from the hardware modules to a soft-core processor, MicroBlaze, for computation of distance and angle. A CMOS imaging sensor operating at a clock frequency of 27MHz was used in our experiments to produce a video stream at the rate of 75 frames per second. Image component labeling and feature extraction modules were running in parallel having a total latency of 13ms. The MicroBlaze was interfaced with the component labeling and feature extraction modules through Fast Simplex Link (FSL). The latency for computing distance and angle of camera from the reference points was measured to be 2ms on the MicroBlaze, running at 100 MHz clock frequency. In this paper, we present the performance analysis, device utilization and power consumption for the designed system. The FPGA based machine vision system that we propose has high frame speed, low latency and a power consumption that is much lower compared to commercially available smart camera solutions. © 2012 SPIE.

Place, publisher, year, edition, pages
SPIE - International Society for Optical Engineering, 2012
Keywords
Component labeling; Machine vision; Smart camera
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-16697 (URN)10.1117/12.927854 (DOI)000305693900028 ()2-s2.0-84861951577 (Scopus ID)STC (Local ID)978-081949129-9 (ISBN)STC (Archive number)STC (OAI)
Conference
Real-Time Image and Video Processing 2012;Brussels;19 April 2012through19 April 2012;Code90041
Available from: 2012-08-10 Created: 2012-08-10 Last updated: 2016-10-20Bibliographically approved
5. Portability Analysis of Soft Microprocessor for FPGA
Open this publication in new window or tab >>Portability Analysis of Soft Microprocessor for FPGA
2012 (English)In: 2012 Mediterranean Conference on Embedded Computing, MECO 2012, IEEE conference proceedings, 2012, p. 5-8Conference paper, Published paper (Refereed)
Abstract [en]

This paper discusses the portability issues of soft microprocessor used on FPGA platform. The problems of maintaining a long life cycle system related to soft microprocessor’s portability is emphasized. Three soft microprocessors’ portability was analyzed in the experiments, which represent three types of soft microprocessor groups. The result shows that the system with commercial licensed vendor independent soft microprocessor possesses higher portability and reliability and it is the preferred alternative for designing a long life cycle system. The result from the paper can give guidance to the designers who suffer from microprocessor obsolescence problems.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2012
Keywords
soft microprocessor; portability; FPGA; long life cycle
National Category
Embedded Systems
Identifiers
urn:nbn:se:miun:diva-16402 (URN)2-s2.0-84866972381 (Scopus ID)STC (Local ID)978-1-4673-2366-6 (ISBN)STC (Archive number)STC (OAI)
Conference
1st Mediterranean Conference on Embedded Computing, MECO 2012;Bar;19 June 2012through21 June 2012;Category numberCFP11CBM-ART;Code93002
Available from: 2012-06-10 Created: 2012-06-10 Last updated: 2016-10-20Bibliographically approved
6. Component obsolescence management model for long life cycle embedded system
Open this publication in new window or tab >>Component obsolescence management model for long life cycle embedded system
2012 (English)In: AUTOTESTCON (Proceedings), Anaheim, California: IEEE conference proceedings, 2012, p. 19-24Conference paper, Published paper (Refereed)
Abstract [en]

This paper discusses the component obsolescence problem and presents a mathematic model for life cycle analysis of long life cycle embedded system maintenance. This model can estimate minimized management costs for different system architecture. Matlab is used to generate a graph and Lingo is used for linear programming. A simple CAN controller system case study is shown to apply this model. A minimized management cost and an optimized management time schedule are given as the result. The responses from the experiments of the model meet our expectation. Although the model has lots of simplifications and limitations, it can give management strategy guidance to the designers who suffer from component obsolescence problems. 

Place, publisher, year, edition, pages
Anaheim, California: IEEE conference proceedings, 2012
Keywords
model, obsolescence management, long life cycle, embedded system
National Category
Embedded Systems
Identifiers
urn:nbn:se:miun:diva-16438 (URN)10.1109/AUTEST.2012.6334547 (DOI)2-s2.0-84869792681 (Scopus ID)STC (Local ID)978-146730699-7 (ISBN)STC (Archive number)STC (OAI)
Conference
48th IEEE Systems Readiness Technology Conference, AUTOTESTCON 2012; 10-13 Sep 2012; Anaheim,USA
Note

Best student paper

Available from: 2012-06-14 Created: 2012-06-14 Last updated: 2016-10-20Bibliographically approved
7. Strategic Proactive Obsolescence Management Model
Open this publication in new window or tab >>Strategic Proactive Obsolescence Management Model
2014 (English)In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 4, no 6, p. 1099-1108Article in journal (Refereed) Published
Abstract [en]

When there is a demand larger than the corresponding number of components in stock, obsolescence problems may occur for those systems with a life cycle longer than that of one or more of their components, such as automotive, avionics, military application, etc. This paper discusses the electronic component obsolescence problem and presents a formal mathematical strategic proactive obsolescence management model for long life cycle systems.

The model presented in this paper utilizes redesign and last-time-buy (LTB) as two management methods. LTB cost is estimated by unit cost, demand quantities, buffer, discount rate and holding cost. Redesign cost is associated with component type and quantities.

This model can estimate the minimum management costs for a system with different architectures. It consists of two parts. The first is to generate a graph, which is in the form of an obsolescence management diagram. A segments table containing the data of this diagram is calculated and prepared for optimization at a second step. This second part is to find the minimum cost for system obsolescence management. Mixed integer linear programming (MILP) is used to calculate the minimum management cost and schedule. The model is open sourced allowing other research groups to freely download and modify it.

A display and control system case study is shown to apply this model practically. A reactive manner is presented as a comparison. The result of the strategic proactive management model shows significant cost avoidance as compared to the reactive manner.

Place, publisher, year, edition, pages
IEEE Components, Packaging, and Manufacturing Technology Society, 2014
Keywords
Strategic; DMSMS; Obsolescence; Graph; MILP
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-21016 (URN)10.1109/TCPMT.2014.2316212 (DOI)000337136200017 ()2-s2.0-84902144517 (Scopus ID)STC (Local ID)STC (Archive number)STC (OAI)
Available from: 2014-01-12 Created: 2014-01-12 Last updated: 2017-12-06
8. Design Technology Selection for Obsolescence Management Cost Avoidanc
Open this publication in new window or tab >>Design Technology Selection for Obsolescence Management Cost Avoidanc
(English)Manuscript (preprint) (Other academic)
Abstract [en]

Component obsolescence problems may occur in systems with a life cycle longer than that of one or more of their components, such as automotive, avionics, military application, etc. This paper presents how the design technology selection will impact upon obsolescence management costs for a long life cycle system. Several hardware platforms such as commercial off-the-shelf (COTS) and FPGA are discussed. FPGA design technology is emphasized, and intellectual property (IP) portability is discussed which would affect the redesign costs for obsolescence management. Moreover, embedded software is also a crucial part in relation to long life cycle system sustainment.

An industrial display computer system is used as an experimental system for a case study. Early cost estimation is carried out before the system development. The proposed FPGA system with device independent IPs indicates a cost avoidance of more than 75% compared to the original COTS based system.

Keywords
Long life cycle; Obsolescence management; FPGA; IP; Portability
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-21677 (URN)
Available from: 2014-04-03 Created: 2014-04-03 Last updated: 2016-12-09Bibliographically approved

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