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Portability analysis of an M-JPEG decoder IP from OpenCores
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)ORCID iD: 0000-0002-3429-273X
2011 (English)In: SIES 2011 - 6th IEEE International Symposium on Industrial Embedded Systems, Conference Proceedings, IEEE conference proceedings, 2011, 79-82 p.Conference paper, Published paper (Refereed)
Abstract [en]

The reuse of predefined Intellectual Property (IP) can shorten development times and help the designer to meet time-to-market requirements for embedded systems. Using FPGA IP in a proper way can also mitigate the component obsolescence problem. System migration between devices is unavoidable, especially for long lifetime embedded systems, so IP portability becomes an important issue for system maintenance. This paper presents a case study analyzing the portability of an FPGA-based M-JPEG decoder IP. The lack of any clear separation between computation and communication is shown to limit the decoder's portability with respect to different communication interfaces. Technology and tool dependent firmware IP components are often supplied by FPGA vendors. It is possible for these firm IP components to reduce development time. However, the use of these technology and tool dependent firmware specifications within the M-JPEG decoder is shown to limit the decoder's portability with respect to development tools and FPGA vendors.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011. 79-82 p.
Keyword [en]
IP, FPGA, obsolescence, maintenance, portability, M-JPEG decoder
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-14310DOI: 10.1109/SIES.2011.5953685Scopus ID: 2-s2.0-80052019062Local ID: STCISBN: 978-1-61284-819-8 (print)ISBN: 978-1-61284-818-1 (print)OAI: oai:DiVA.org:miun-14310DiVA: diva2:434420
Conference
6th IEEE International Symposium on Industrial Embedded Systems, SIES 2011;Vasteras;15 June 2011through17 June 2011;Category numberCFP11INB-ART;Code86076
Projects
STC
Available from: 2011-08-15 Created: 2011-08-15 Last updated: 2016-10-19Bibliographically approved
In thesis
1. Maintenance Consideration for Long Life Cycle Embedded System
Open this publication in new window or tab >>Maintenance Consideration for Long Life Cycle Embedded System
2012 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

     In this thesis, the work presented is in relation to consideration to the maintenance of a long life cycle embedded system. Various issues can present problems for maintaining a long life cycle embedded system, such as component obsolescence and IP (intellectual property) portability.      For products including automotive, avionics, military application etc., the desired life cycles for these systems are many times longer than the obsolescence cycle for the electronic components used in the systems. The maintainability is analyzed in relation to long life cycle embedded systems for different design technologies. FPGA platform solutions are proposed in order to ease the system maintenance. Different platform cases are evaluated by analyzing the essence of each case and the consequences of different risk scenarios during system maintenance. This has shown that an FPGA platform with a vendor and device independent soft IP has the highest maintainability.A mathematic model of obsolescence management for long life cycle embedded system maintenance is presented. This model can estimate the minimum management costs for the different system architecture and this consists of two parts. The first is to generate a graph in Matlab which is in the form of state transfer diagram. A segments table is then output from Matlab for further optimization. The second part is to find the lowest cost in the state transfer diagram, which can be viewed as a transshipment problem. Linear programming is used to calculate the minimized management cost and schedule, which is solved by Lingo. A simple Controller Area Network (CAN) controller system case study is shown in order to apply this model. The model is validated by a set of synthetic and experimentally selected values. The results provided by this are a minimized management cost and an optimized management time schedule. Test experiments of the maintenance cost responding to the interest rate and unit cost are implemented. The responses from the experiments meet our expectations.      The reuse of predefined IP can shorten development times and assist the designer to meet time-to-market (TTM) requirements. System migration between devices is unavoidable, especially when it has a long life cycle expectation, so IP portability becomes an important issue for system maintenance. An M-JPEG decoder case study is presented in the thesis. The lack of any clear separation between computation and communication is shown to limit the IP’s portability with respect to different communication interfaces. A methodology is proposed to ease the interface modification and interface reuse, thus to increase the portability of an IP. Technology and tool dependent firmware IP components are also shown to limit the IP portability with respect to development tools and FPGA vendors.

Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2012
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 81
National Category
Embedded Systems
Identifiers
urn:nbn:se:miun:diva-16440 (URN)STC (Local ID)978-91-87103-14-8 (ISBN)STC (Archive number)STC (OAI)
Supervisors
Available from: 2012-06-14 Created: 2012-06-14 Last updated: 2016-10-20Bibliographically approved
2. Technology Driven Obsolescence Management for Embedded Systems
Open this publication in new window or tab >>Technology Driven Obsolescence Management for Embedded Systems
2014 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, the work presented is in relation to technology driven obsolescence management for embedded systems.

Component obsolescence problems may occur in systems with a life cycle longer than that of one or more of their components when there is a demand without enough existing stock, such as automotive, avionics, military applications, etc. This thesis analyzes the component obsolescence problem from both the design technology selection and management perspectives.

Design technologies selection is associated with hardware and software. Several hardware platforms such as COTS and field-programmable gate array (FPGA) are discussed. FPGA intellectual property (IP) portability is emphasized which will affect the obsolescence management cost. Embedded software is also a crucial part for system sustainment. A risk analysis is performed in relation to long life cycle systems for different design technologies. Different platform cases are evaluated by analyzing the essence of each case and the consequences of different risk scenarios during system maintenance. This has shown that an FPGA platform with the vendor and device independent soft IPs has the highest maintainability and the minimum redesign cost.

The reuse of a predefined IP can shorten the development times and assist the designer to meet time-to-market (TTM) requirements. System migration between devices is unavoidable, especially when it has a long life cycle expectation, so IP portability becomes an important issue for system maintenance. If an IP for FPGAs is truly portable, it must be easily adaptable to different communication interfaces, being portable between different FPGA vendors and devices, having no dependencies on the tool set and library used for the system design and no restriction on the communication interface. An M-JPEG decoder and a soft microprocessor portability analysis case study are presented in the thesis. A methodology is proposed to ease the interface modification and interface reuse, thus to increase the portability of an IP.

A strategic proactive obsolescence management model is proposed from a management perspective. This model can estimate the minimum management costs for a system with different architectures. It consists of two parts. The first is to generate a graph, which is in the form of an obsolescence management diagram. A segments table containing the data of this diagram is calculated and prepared for optimization at a second step. This second part is to find the minimum cost for system obsolescence management. Mixed integer linear programming (MILP) is used to calculate the minimum management cost and schedule. The model is open sourced thus allowing other research groups to freely download and modify it.

Both the design technology selection and the strategic proactive obsolescence management are demonstrated by an industrial display computer system case study. The results show significant cost avoidance as compared to the original method used by the company.

Finally, the research results are encapsulated into an obsolescence management cost avoidance methodology.  

Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2014. 178 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 186
Keyword
Long life cycle, embedded system, DMSMS, obsolescnece, FPGA, IP, portability
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-21744 (URN)STC (Local ID)978-91-87557-50-7 (ISBN)STC (Archive number)STC (OAI)
Public defence
2014-05-15, O102, Sundsvall, 11:17 (English)
Opponent
Supervisors
Funder
Knowledge Foundation
Available from: 2014-04-17 Created: 2014-04-11 Last updated: 2017-03-06Bibliographically approved

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Citation style
  • apa
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