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D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics design division)
Department of Informatics, University of Oslo.
Responsible organisation
2007 (English)In: 2007 NORCHIP, IEEE conference proceedings, 2007, p. 146-149Conference paper, Published paper (Refereed)
Abstract [en]

When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2007. p. 146-149
Keywords [en]
Subthreshold, Floating-gate, digital, latch, low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-4451ISI: 000257311000034Scopus ID: 2-s2.0-50249139531Local ID: 5436ISBN: 978-1-4244-1516-8 (print)OAI: oai:DiVA.org:miun-4451DiVA, id: diva2:29483
Conference
25th Norchip Conference, Nov 19-20, 2007, Aalborg, Denmark
Projects
STC - Sensible Things that CommunicateAvailable from: 2009-01-07 Created: 2009-01-07 Last updated: 2017-10-18Bibliographically approved
In thesis
1. Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
Open this publication in new window or tab >>Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2008. p. 129
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 54
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7567 (URN)978-91-85317-97-4 (ISBN)
Public defence
(English)
Supervisors
Available from: 2008-12-10 Created: 2008-12-10 Last updated: 2011-02-06Bibliographically approved

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Alfredsson, Jon

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CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf