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Power-aware automatic constraint generation for FPGA based real-time video processing systems
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics design division)ORCID iD: 0000-0002-3429-273X
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
Responsible organisation
2007 (English)In: 2007 NORCHIP, New York: IEEE conference proceedings, 2007, 124-128 p.Conference paper, (Refereed)
Abstract [en]

The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.

Place, publisher, year, edition, pages
New York: IEEE conference proceedings, 2007. 124-128 p.
Keyword [en]
FPGA
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-4375DOI: 10.1109/NORCHP.2007.4481054ISI: 000257311000029Local ID: 5278ISBN: 978-1-4244-1516-8 (print)OAI: oai:DiVA.org:miun-4375DiVA: diva2:29407
Conference
25th Norchip Conference, Nov 19-20, 2007, Aalborg, Denmark
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2013-03-25Bibliographically approved
In thesis
1. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance.

Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ., 2009. 180 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 66
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7697 (URN)978-91-86073-26-8 (ISBN)
Public defence
2009-01-07, O102, Mittuniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things that Communicate
Note
Electronics design divisionAvailable from: 2008-12-19 Created: 2008-12-11 Last updated: 2011-02-06Bibliographically approved

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Citation style
  • apa
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Output format
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