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Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
Responsible organisation
2006 (English)In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, 1296-1299 p.Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

Place, publisher, year, edition, pages
2006. 1296-1299 p.
Keyword [en]
Low Power, Digital CMOS, Floating-gate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-3899DOI: 10.1109/ICECS.2006.379719ISI: 000252489600324Local ID: 4257ISBN: 978-1-4244-0394-3 (print)OAI: oai:DiVA.org:miun-3899DiVA: diva2:28931
Conference
13th IEEE International Conference on Electronics, Circuits and Systems, Dec 10-13, 2006, Nice, France
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2011-02-06Bibliographically approved
In thesis
1. Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
Open this publication in new window or tab >>Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2008. 129 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 54
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7567 (URN)978-91-85317-97-4 (ISBN)
Public defence
(English)
Supervisors
Available from: 2008-12-10 Created: 2008-12-10 Last updated: 2011-02-06Bibliographically approved
2. Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
Open this publication in new window or tab >>Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
2007 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

All who is involved in electronic design knows that one of the critical issues

in today’s electronic is the power consumption. Designers are always looking for

new approaches in order to reduce currents while still retain performance.

Floating-gate (FGMOS) circuits have previously been shown to be a promising

technique to improve speed and still keep the power consumption low when

power supply is reduced below subthreshold voltage for the transistors.

In this thesis, the goal is to determine how good floating-gate circuits can be

compared to conventional static CMOS when the circuits are working in

subthreshold. The most interesting performance parameters are speed and power

consumption and specifically the Energy-Delay Product (EDP) that is a

combination of those two. To get a view over how the performance varies and how

good the FGMOS circuits are at their best case, the circuits have been designed and

simulated for best case performance.

The investigation also includes trade-offs with speed and power

consumption for better performance, how to select floating-gate capacitances, how

a large circuit fan-in will affect performance and also the influence of different

kinds of refresh circuits.

The first simulations of the FGMOS circuits in a 0.13 μm process have

several interesting results. First of all, in the best case it is shown that FGMOS has

potential to achieve up to 260 times in better EDP-performance compared to CMOS

at 150 mV power supply. Continuing with simulations of FGMOS capacitances

shows that minimum floating-gate capacitance can be as small as 400 fF and more

realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

capacitances included). Other aspects of FGMOS design have been to look at how

refresh circuits will affect performance (semi-floating-gate circuits) and how a

larger fan-in will change noise margin and EDP. It turns out that refresh circuits

with the same transistor size does not give a noticeable change in performance

while an increase of 8 times in size will give between 5 and 10 times wors EDP.

When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

150 mV.

Finally, it should be kept in mind that tuning the performance of FGMOS

circuits with trade-offs and by changing the floating-gate voltages to achieve

results like the ones stated above will also always affect the noise margins, NM, of

the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

fabricated circuit with that NM may not be as functional as simulations suggests.

The probability to design functional FGMOS circuits in subthreshold does not

seem to be a problem though.

Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet, 2007. 44 p.
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 18
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-9333 (URN)91-85317-35-7 (ISBN)
Presentation
(English)
Opponent
Supervisors
Available from: 2009-07-10 Created: 2009-07-10 Last updated: 2011-02-06Bibliographically approved

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Alfredsson, JonOelmann, Bengt

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