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Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics design division)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.ORCID iD: 0000-0002-3429-273X
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics design division)
2007 (English)In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, Vol. 2007, 75368Article in journal (Refereed) Published
Abstract [en]

This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

Place, publisher, year, edition, pages
2007. Vol. 2007, 75368
Keyword [en]
Embedded systems, Video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-3879DOI: 10.1155/2007/75368Scopus ID: 2-s2.0-33846809178Local ID: 4203OAI: oai:DiVA.org:miun-3879DiVA: diva2:28911
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2016-10-11Bibliographically approved
In thesis
1. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance.

Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ., 2006. 114 p.
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 14
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7696 (URN)91-85317-30-6 (ISBN)
Presentation
2006-11-22, M102, MittUniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things That Communicate
Available from: 2008-12-19 Created: 2008-12-11 Last updated: 2009-02-13Bibliographically approved
2. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance.

Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ., 2009. 180 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 66
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7697 (URN)978-91-86073-26-8 (ISBN)
Public defence
2009-01-07, O102, Mittuniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things that Communicate
Note
Electronics design divisionAvailable from: 2008-12-19 Created: 2008-12-11 Last updated: 2011-02-06Bibliographically approved
3. Development, analysis and implementation of pre-processing video filters
Open this publication in new window or tab >>Development, analysis and implementation of pre-processing video filters
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The usage of video systems in households and industry has increased rapidly over the past few years. The benefits of visual processing, control and inspection have offered great opportunities for real-time video processing systems (RTVPS) for the general public as well as for heavy industries. The high volume market media systems can absorb a great deal of the cost related to the development of standard components, such as Field Programmable Gate Arrays (FPGAs). The development of industrial systems can benefit from this new technology by utilizing these cheap components. In this thesis, examples of video processing algorithms suitable for pre-processing of digital video applicable for both industrial and media usage will be shown. In addition a methodology supporting the designer in implementing memory architectures suitable for such algorithms is presented. In this thesis two video processing algorithms are presented and described in detail. The common denominator is their utilization of data from temporally adjacent frames in order to be effective, in terms of compression efficiency, and to produce an attractive result for the viewer. However, from the aspect of quality improvement, considerations have to be taken into account in order to enable an actual hardware implementation. Utilizing data from temporally adjacent frames in a real-time data stream is a non-trivial task. From the algorithm designer’s view the data dependencies and memory requirements are not in focus, but for the hardware designer they are. Having the right data available at the right time is the only consideration in order to have a functional system. Present day algorithm and hardware development methods and architectures do not converge into a common design flow, even though this has been attempted. The gap between the algorithm designer and his/her hardware counterpart has to be bridged in order to obtain an efficient and rapid implementation. Methodologies that abstract and reduce the amount of time spent on implementing memory architectures for video processing applications are required. The buffering requirements are often too complex to analyze manually in order to efficiently utilize the resources available in FPGAs. In this thesis a method for the synthesis and implementation of memory architectures for real-time video processing systems, IMapper, is presented. The architecture supports the implementation of spatio- and temporal video processing algorithms and utilizes methodologies for global optimization of on-fabric available memory resources for FPGAs. This methodology provides an efficient and flexible implementation environment and also offers the benefits of the global optimizations it utilizes

Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet, 2006. 116 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 13
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8881 (URN)91-85317-36-5 (ISBN)
Public defence
2006-12-15, Sundsvall, 08:30 (English)
Opponent
Supervisors
Available from: 2009-05-06 Created: 2009-05-06 Last updated: 2009-07-13Bibliographically approved

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