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Ram allocation algorithm for video processing applications on FPGA
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.ORCID iD: 0000-0002-3429-273X
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
Responsible organisation
2006 (English)In: Journal of Circuits, Systems and Computers, ISSN 0218-1266, Vol. 15, no 5, 679-699 p.Article in journal (Refereed) Published
Abstract [en]

This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.

Place, publisher, year, edition, pages
2006. Vol. 15, no 5, 679-699 p.
Keyword [en]
Allocation algorithm, FPGA, Global block RAM, Real-time, Video processing system
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-3849DOI: 10.1142/S0218126606003295ISI: 000244309500003Scopus ID: 2-s2.0-33846524776Local ID: 4105OAI: oai:DiVA.org:miun-3849DiVA: diva2:28881
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2016-10-03Bibliographically approved
In thesis
1. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance.

Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ., 2006. 114 p.
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 14
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7696 (URN)91-85317-30-6 (ISBN)
Presentation
2006-11-22, M102, MittUniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things That Communicate
Available from: 2008-12-19 Created: 2008-12-11 Last updated: 2009-02-13Bibliographically approved
2. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance.

Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ., 2009. 180 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 66
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7697 (URN)978-91-86073-26-8 (ISBN)
Public defence
2009-01-07, O102, Mittuniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things that Communicate
Note
Electronics design divisionAvailable from: 2008-12-19 Created: 2008-12-11 Last updated: 2011-02-06Bibliographically approved

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