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Simplified Gate Level Noise Injection Models for Behavioral Noise Coupling Simulation
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics design division)
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
2005 (English)In: Proceedings of the 2005 European Conference on Circuit Theory and Design: 28 Aug.-2 Sept. 2005, Cork, Ireland, Piscataway, NJ, USA: IEEE conference proceedings, 2005, Vol. 3, 345-348 p., 1523131Conference paper, (Refereed)
Abstract [en]

In CMOS digital logic, there are two major noise sources requiring consideration. These are a circuit´s power supply current and its noise current injected into the substrate of the circuit. This paper proposes a method for modeling and estimating the noise current injected into the substrate by capacitive coupling in digital circuits. The simplicity of the model and the reduction of details in the technology libraries facilitates behavioral level noise coupling simulation. The model is exemplified and evaluated for a simple NOT gate test case, for which the accuracy and simplicity of the models show great promise for simulation at the behavioral level.

Place, publisher, year, edition, pages
Piscataway, NJ, USA: IEEE conference proceedings, 2005. Vol. 3, 345-348 p., 1523131
Keyword [en]
Injection models, Behavioral, Noise Coupling
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-3366DOI: 10.1109/ECCTD.2005.1523131Scopus ID: 2-s2.0-33749034204Local ID: 3337ISBN: 0780390660 (print)ISBN: 978-078039066-9 OAI: oai:DiVA.org:miun-3366DiVA: diva2:28398
Conference
2005 European Conference on Circuit Theory and Design; Cork; Ireland; 28 August 2005 through 2 September 2005
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2016-09-29Bibliographically approved
In thesis
1. Simulating Behavioral Level On-Chip Noise Coupling
Open this publication in new window or tab >>Simulating Behavioral Level On-Chip Noise Coupling
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, noise coupling simulation is introduced into the behavioral level. Methods andmodels for simulating on-chip noise coupling at the behavioral level in a design flow are presentedand verified for accuracy and validity. Today, designs of electronic systems are becoming denserand more and more mixed-signal systems such as System-on-Chip (SoC) are being devised. Thisraises problems when the electronics components start to interfere with each other. Often, digitalcomponents disturb analog components, introducing noise into the system causing degradation ofthe performance or even introducing errors into the functionality of the system.Today, these effects can only be simulated at a very late stage in the design process, causinglarge design iterations and increased costs if the designers are required to return and makealterations, which may have occurred at a very early stage in the process.This is why the focus of this work is centered on extracting noise coupling simulation modelsthat can be used at a very early design stage, such as at the behavioral level and then follow thedesign through the various design stages. To achieve this, SystemC is selected as a platform andimplementation example for the behavioral level models. SystemC supports design refinement,which means that when designs are being refined and are crossing the design levels, the noisecoupling models can also be refined to suit the current design.This new method of thinking in primarily mixed-signal designs is called Behavioral levelNoise Coupling (BeNoC) simulation and shows great promise in enabling a reduction in the costsof design iterations due to component cross-talk and simplifies the work for mixed-signal systemdesigners.

Abstract [sv]

I denna avhandling introduceras brussimulering i mikrochip på en beteendenivå. Metoderoch modeller för brussimulering i chip presenteras och verifieras för noggrannhet och funktionalitetpå en beteendenivå i designflödet. I dagsläget blir elektroniska system tätare och tätare på chippenoch fler och fler system görs med både analog och digital elektronik såsom System-on-Chip (SoC).Detta skapar problem när komponenter börjar störa varandra. Oftast är det digitala komponentersom stör de analoga, vilket introducerar brus i systemet som reducerar prestanda eller till och medinför fel i funktionen hos systemet.Idag kan dessa effekter simuleras i ett mycket sent skede i designflödet, betyder att om felupptäcks måste designern kanske gå tillbaka många steg i flödet. Detta kostar mycket tid ochpengar.Därför ligger fokus i detta arbete på att extrahera brussimuleringsmodeller som kananvändas i ett tidigt skede såsom på beteendenivå och sedan följa designen genom senare skeden idesignflödet. För att realisera detta har SystemC valts som en plattform och som ettimplementationsexempel för beteendenivåmodellerna. SystemC har stöd för förfining av designervilket betyder att ett system kan börja beskrivas på en hög nivå för att sedan förfinas för att nå lägrenivåer. Detta gör det möjligt för brusmodellerna att också förfinas i takt med systemdesignen.Detta nya sätt att tänka på i designprocessen av i huvudsak analog/digital-integreradesystem kallas Behavioral level Noise Coupling (BeNoC) simulering och bådar gott för att reducerakostnader för designiterationer på grund av brus mellan komponenter, och gör arbetet enklare föranalog/digital- (mixed-signal) designers.

Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2007. 151 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 25
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8057 (URN)978-91-85317-54-7 (ISBN)
Public defence
2007-05-30, O102, Holmgatan 10, Sundsvall, 10:00 (English)
Opponent
Supervisors
Available from: 2009-01-12 Created: 2009-01-07 Last updated: 2011-02-06Bibliographically approved

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Citation style
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