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Spatio-Temporal Noise Reduction algorithm targeting Real-Time Video Processing
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
2000 (English)In: Proceedings of IEEE International Symposium on Information Theory and Its Applications 2000, 2000Conference paper, (Refereed)
Place, publisher, year, edition, pages
2000.
Keyword [en]
Noise reduction Real-Time Video
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-1651Local ID: 272OAI: oai:DiVA.org:miun-1651DiVA: diva2:26683
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2011-04-19Bibliographically approved
In thesis
1. Development, analysis and implementation of pre-processing video filters
Open this publication in new window or tab >>Development, analysis and implementation of pre-processing video filters
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The usage of video systems in households and industry has increased rapidly over the past few years. The benefits of visual processing, control and inspection have offered great opportunities for real-time video processing systems (RTVPS) for the general public as well as for heavy industries. The high volume market media systems can absorb a great deal of the cost related to the development of standard components, such as Field Programmable Gate Arrays (FPGAs). The development of industrial systems can benefit from this new technology by utilizing these cheap components. In this thesis, examples of video processing algorithms suitable for pre-processing of digital video applicable for both industrial and media usage will be shown. In addition a methodology supporting the designer in implementing memory architectures suitable for such algorithms is presented. In this thesis two video processing algorithms are presented and described in detail. The common denominator is their utilization of data from temporally adjacent frames in order to be effective, in terms of compression efficiency, and to produce an attractive result for the viewer. However, from the aspect of quality improvement, considerations have to be taken into account in order to enable an actual hardware implementation. Utilizing data from temporally adjacent frames in a real-time data stream is a non-trivial task. From the algorithm designer’s view the data dependencies and memory requirements are not in focus, but for the hardware designer they are. Having the right data available at the right time is the only consideration in order to have a functional system. Present day algorithm and hardware development methods and architectures do not converge into a common design flow, even though this has been attempted. The gap between the algorithm designer and his/her hardware counterpart has to be bridged in order to obtain an efficient and rapid implementation. Methodologies that abstract and reduce the amount of time spent on implementing memory architectures for video processing applications are required. The buffering requirements are often too complex to analyze manually in order to efficiently utilize the resources available in FPGAs. In this thesis a method for the synthesis and implementation of memory architectures for real-time video processing systems, IMapper, is presented. The architecture supports the implementation of spatio- and temporal video processing algorithms and utilizes methodologies for global optimization of on-fabric available memory resources for FPGAs. This methodology provides an efficient and flexible implementation environment and also offers the benefits of the global optimizations it utilizes

Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet, 2006. 116 p.
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 13
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8881 (URN)91-85317-36-5 (ISBN)
Public defence
2006-12-15, Sundsvall, 08:30 (English)
Opponent
Supervisors
Available from: 2009-05-06 Created: 2009-05-06 Last updated: 2009-07-13Bibliographically approved
2. Pre-Processing Video Filters and Automated Implementation of Memory Architectures
Open this publication in new window or tab >>Pre-Processing Video Filters and Automated Implementation of Memory Architectures
2005 (English)Licentiate thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet, 2005. 74 p.
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 4
Keyword
Pre-Processing Video Implementation Memory Arhchitectures
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-5792 (URN)3153 (Local ID)91-85317-04-7 (ISBN)3153 (Archive number)3153 (OAI)
Presentation
(English)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2009-07-10Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • harvard1
  • ieee
  • modern-language-association-8th-edition
  • vancouver
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More styles
Language
  • de-DE
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  • en-US
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  • sv-SE
  • Other locale
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Output format
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  • asciidoc
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