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Multi-phase validation of hardware/software interfaces based on generated simulation models
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
1998 (English)In: IEEE International High Level Design Validation and Test Workshop : Sheraton Grande Torrey Pinnes, La Jolla, California, November 12 - 14, 1998; [digest of papers] / HLDVT-98: HLDVT-98, [LaJolla, Calif.]: IEEE , 1998, 218- p.Conference paper, (Refereed)
Abstract [en]

Hardware/Software interfaces are a critical point for system simulation because the hardware and software parts are developed by separate development activities. Our multi-phase validation approach facilitates the simulation of the interfaces at several steps during development. We keep all the simulation models consistent with both the specification and the implementation by generating the models with a technique derived from interface synthesis, that enables the interface specification, simulation models, and implementation to be consistent with each other. We justify validation in several phases by (a) the up to four orders of magnitude faster simulation of early phases compared to late phases, and by (b) allowing both HW designer and SW developers to work in their familiar tool environment as long as possible.

Place, publisher, year, edition, pages
[LaJolla, Calif.]: IEEE , 1998. 218- p.
Keyword [en]
validation, hw/sw interfaces, hw/sw codesign
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-1494Local ID: 615OAI: oai:DiVA.org:miun-1494DiVA: diva2:26526
Available from: 2008-09-30 Created: 2008-09-30Bibliographically approved

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CiteExportLink to record
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Citation style
  • apa
  • ieee
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  • de-DE
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Output format
  • html
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