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Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics Design Division, STC)
2007 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

All who is involved in electronic design knows that one of the critical issues

in today’s electronic is the power consumption. Designers are always looking for

new approaches in order to reduce currents while still retain performance.

Floating-gate (FGMOS) circuits have previously been shown to be a promising

technique to improve speed and still keep the power consumption low when

power supply is reduced below subthreshold voltage for the transistors.

In this thesis, the goal is to determine how good floating-gate circuits can be

compared to conventional static CMOS when the circuits are working in

subthreshold. The most interesting performance parameters are speed and power

consumption and specifically the Energy-Delay Product (EDP) that is a

combination of those two. To get a view over how the performance varies and how

good the FGMOS circuits are at their best case, the circuits have been designed and

simulated for best case performance.

The investigation also includes trade-offs with speed and power

consumption for better performance, how to select floating-gate capacitances, how

a large circuit fan-in will affect performance and also the influence of different

kinds of refresh circuits.

The first simulations of the FGMOS circuits in a 0.13 μm process have

several interesting results. First of all, in the best case it is shown that FGMOS has

potential to achieve up to 260 times in better EDP-performance compared to CMOS

at 150 mV power supply. Continuing with simulations of FGMOS capacitances

shows that minimum floating-gate capacitance can be as small as 400 fF and more

realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

capacitances included). Other aspects of FGMOS design have been to look at how

refresh circuits will affect performance (semi-floating-gate circuits) and how a

larger fan-in will change noise margin and EDP. It turns out that refresh circuits

with the same transistor size does not give a noticeable change in performance

while an increase of 8 times in size will give between 5 and 10 times wors EDP.

When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

150 mV.

Finally, it should be kept in mind that tuning the performance of FGMOS

circuits with trade-offs and by changing the floating-gate voltages to achieve

results like the ones stated above will also always affect the noise margins, NM, of

the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

fabricated circuit with that NM may not be as functional as simulations suggests.

The probability to design functional FGMOS circuits in subthreshold does not

seem to be a problem though.

Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet , 2007. , p. 44
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 18
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-9333ISBN: 91-85317-35-7 (print)OAI: oai:DiVA.org:miun-9333DiVA, id: diva2:227257
Presentation
(English)
Opponent
Supervisors
Available from: 2009-07-10 Created: 2009-07-10 Last updated: 2011-02-06Bibliographically approved
List of papers
1. Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
Open this publication in new window or tab >>Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
2005 (English)In: Proceedings of IFIP VLSI-SOC 2005: International Conference on Very Large Scale Integration, Edith Cowan Univ , 2005, p. 229-232Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

Place, publisher, year, edition, pages
Edith Cowan Univ, 2005
Keywords
low power electronics subthreshold floating-gate
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8006 (URN)
Conference
IFIP International Conference on Very Large Scale Interaction
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2012-02-16Bibliographically approved
2. Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold
Open this publication in new window or tab >>Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold
2006 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, IEEE conference proceedings, 2006, p. 4341-4344, article id 1693590Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

Place, publisher, year, edition, pages
IEEE conference proceedings, 2006
Series
IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, ISSN 0277-674X
Keywords
low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3743 (URN)10.1109/ISCAS.2006.1693590 (DOI)000245413504168 ()2-s2.0-34547241637 (Scopus ID)4017 (Local ID)978-0-7803-9389-9 (ISBN)4017 (Archive number)4017 (OAI)
Conference
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems; Kos; Greece; 21 May 2006 through 24 May 2006
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2016-10-05Bibliographically approved
3. Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs
Open this publication in new window or tab >>Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs
2006 (English)In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 1296-1299Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

Keywords
Low Power, Digital CMOS, Floating-gate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3899 (URN)10.1109/ICECS.2006.379719 (DOI)000252489600324 ()4257 (Local ID)978-1-4244-0394-3 (ISBN)4257 (Archive number)4257 (OAI)
Conference
13th IEEE International Conference on Electronics, Circuits and Systems, Dec 10-13, 2006, Nice, France
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2011-02-06Bibliographically approved
4. Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure
Open this publication in new window or tab >>Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure
2007 (English)In: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, IEEE conference proceedings, 2007, p. 314-317Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

Place, publisher, year, edition, pages
IEEE conference proceedings, 2007
Series
International Conference on VLSI Design, Proceedings, ISSN 1063-9667
Keywords
Low power, Digital CMOS, Floating-gate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3900 (URN)10.1109/VLSID.2007.143 (DOI)000245425300045 ()2-s2.0-48349148523 (Scopus ID)4258 (Local ID)978-0-7695-2762-8 (ISBN)4258 (Archive number)4258 (OAI)
Conference
20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems, jan 06-10, 2007, Bangalore, india
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2017-10-20Bibliographically approved

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