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Automatic Synthesis of Partitioned FSMs Based on Mixed Synchronous/Asynchronous State Memory
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (STC)
2007 (English)Doctoral thesis, comprehensive summary (Other academic)
Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet , 2007. , p. 145
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 20
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-8887ISBN: 978-91-85317-47-9 (print)OAI: oai:DiVA.org:miun-8887DiVA, id: diva2:216077
Public defence
2007-06-15, Sundsvall, 13:15 (English)
Opponent
Supervisors
Available from: 2009-05-06 Created: 2009-05-06 Last updated: 2011-02-06Bibliographically approved
List of papers
1. Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design
Open this publication in new window or tab >>Mixed Synchronous/Asynchronous State Memory for Low Power FSM Design
2004 (English)In: Proceedings of EUROMICRO Symposium on Digital System Design / [ed] Selvaraj, H, IEEE COMPUTER SOC , 2004, p. 363-370Conference paper, Published paper (Refereed)
Abstract [en]

Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on mixed synchronous/asynchronous state memory that results in implementations with low power dissipation and low area overhead for partitioned FSM.s. The state memory here is composed of the synchronous local state memory and asynchronous global state memory, where the former is used to distinguish the states inside a sub-FSM, and the latter is responsible for controlling sub-FSM communication. The input and output behaviour of the decomposed FSM is cycle by cycle equivalent to the undecomposed synchronous FSM. Together with clock gating technique, substantial power reduction can be demonstrated.

Place, publisher, year, edition, pages
IEEE COMPUTER SOC, 2004
Keywords
low-power asynchronous
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2588 (URN)000224458900047 ()1936 (Local ID)0-7695-2203-3 (ISBN)1936 (Archive number)1936 (OAI)
Conference
EUROMICRO Systems on Digital System Design, Aug31-Sep 03, 2004, Rennes, France
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2011-04-08Bibliographically approved
2. Synthesis tool for low-power finite-state machines with mixed synchronous/asynchronous state memory
Open this publication in new window or tab >>Synthesis tool for low-power finite-state machines with mixed synchronous/asynchronous state memory
2006 (English)In: IEE Proceedings - Computers and digital Techniques, ISSN 1350-2387, E-ISSN 1359-7027, Vol. 153, no 4, p. 243-248Article in journal (Refereed) Published
Abstract [en]

An efficient way to obtain finite-state machines (FSMs) with low-power consumption is to partition the machine into two or more sub-FSMs and then use dynamic power management where all sub-FSMs not active are shut down, with the effect of reducing dynamic power dissipation. Thus, FSM partitioning algorithms and register-transfer-level power estimation functions are the main focus of the paper as these are key issues in the design of a computer-aided design tool for synthesis of low-power partitioned FSMs. An implementation architecture is targeted, which is based on both synchronous and asynchronous state memory elements that enable larger power reductions than fully synchronous architectures do. Power reductions of up to 77 have been achieved at a cost of an 18 increase in area.

Keywords
low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3255 (URN)10.1049/ip-cdt:20050048 (DOI)000239333200005 ()2-s2.0-33745725666 (Scopus ID)3217 (Local ID)3217 (Archive number)3217 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
3. Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory
Open this publication in new window or tab >>Low-power state encoding for partitioned FSMs with mixed synchronous/asynchronous state memory
2008 (English)In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 41, no 1, p. 123-134Article in journal (Refereed) Published
Abstract [en]

Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared.

 

 

Keywords
Low-power, partitioned FSMs
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2868 (URN)10.1016/j.vlsi.2007.02.002 (DOI)000250491000013 ()2-s2.0-34548503381 (Scopus ID)2473 (Local ID)2473 (Archive number)2473 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-01-19 Last updated: 2017-12-12Bibliographically approved
4. Asynchronous Modules for the Mixed Synchronous/Asynchronous State Memory in FSM Low-Power Partitioning
Open this publication in new window or tab >>Asynchronous Modules for the Mixed Synchronous/Asynchronous State Memory in FSM Low-Power Partitioning
(English)Manuscript (preprint) (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-9374 (URN)
Note
Submitted to Journal of Circuits, Systems and ComputersAvailable from: 2009-07-13 Created: 2009-07-13 Last updated: 2010-01-14Bibliographically approved
5. Area-Power Trade-Off in FSM Partitioning
Open this publication in new window or tab >>Area-Power Trade-Off in FSM Partitioning
2006 (English)In: ICSES'06 - International Conference on Signals and Electronic Systems, Proceedings, 2006, p. 349-352Conference paper, Published paper (Refereed)
Abstract [en]

Finite State Machine (FSM) partitioning together with a Dynamic Power Management (DPM) scheme is an efficient method for low-power FSM design. Taking both power and area into account at an early stage of FSM partitioning is important for choosing an efficient partitioning in terms of both power and area. There are certain FSMs that a partitioning solution with the lowest power has a big area overhead. For them, exploring the area-power trade-off is especially helpful for finding an alternative partitioning with slightly higher power consumption but much lower area. In this paper, we explore the area-power trade-off in FSM partitioning and propose the area cost functions that are verified by correlation coefficient. A relative comparison of the estimated area cost among the partitioning solutions gives the user more freedom to trade power for area. Since the gate-level implementation is unknown, the area constraint should be given in relative terms, not as the specific percentage of area increase allowed

Keywords
Area-Power trade-off, FSM partitioning
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-4061 (URN)2-s2.0-58449092840 (Scopus ID)4571 (Local ID)8392117263 (ISBN)978-839211726-1 (ISBN)4571 (Archive number)4571 (OAI)
Conference
International Conference on Signals and Electronic Systems, ICSES'06; Lodz; Poland; 17 September 2006 through 20 September 2006; Code 74996
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2016-09-26Bibliographically approved
6. The Analysis of Power-Related Characteristics of FSM Benchmarks
Open this publication in new window or tab >>The Analysis of Power-Related Characteristics of FSM Benchmarks
2007 (English)In: 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3, New York: IEEE conference proceedings, 2007, p. 787-790Conference paper, Published paper (Refereed)
Abstract [en]

Benchmarking is a common way to evaluate the effectiveness of finite state machine (FSM) low-power methodologies. The serious problem in the existing standard benchmarks is that power-related characteristics are not provided, and therefore these benchmarks are not complete for reliable evaluation and comparison of low-power methods and tools. To address this problem, this paper introduces the coefficient of variation, which is very useful for quantitative analysis of power-related features of an FSM, and for indicating the power optimization opportunity of the corresponding circuit. Based on the coefficient of variation, input-sensitivity analysis of the whole standard benchmark set is conducted. It reveals that the benchmark set is input-data dependant, and the set is insufficient for low-power FSM researches due to the limited coverage of power-related characteristics.

Place, publisher, year, edition, pages
New York: IEEE conference proceedings, 2007
Series
Midwest Symposium on Circuits and Systems Conference Proceedings, ISSN 1548-3746 ; 9
Keywords
fsm benchmark low-power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-4307 (URN)10.1109/MWSCAS.2007.4488695 (DOI)000257110900168 ()2-s2.0-51449097515 (Scopus ID)5123 (Local ID)978-1-4244-1175-7 (ISBN)5123 (Archive number)5123 (OAI)
Conference
50th Midwest Symposium on Circuits and Systems, Sep 05, 2007-Aug 08, 2008, Montreal, Canada
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-10-18Bibliographically approved
7. A Mixed Synchronous/Asynchronous Design Approach for Fine-Grained Dynamic
Open this publication in new window or tab >>A Mixed Synchronous/Asynchronous Design Approach for Fine-Grained Dynamic
2007 (English)In: Brain Inspired Nano Architectures 2007, World Scientific, 2007Chapter in book (Other academic)
Place, publisher, year, edition, pages
World Scientific, 2007
Keywords
Mixed Synchronous Asynchronous Design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-4065 (URN)4578 (Local ID)4578 (Archive number)4578 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2011-12-22Bibliographically approved

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