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Development, analysis and implementation of pre-processing video filters
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.
2006 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

The usage of video systems in households and industry has increased rapidly over the past few years. The benefits of visual processing, control and inspection have offered great opportunities for real-time video processing systems (RTVPS) for the general public as well as for heavy industries. The high volume market media systems can absorb a great deal of the cost related to the development of standard components, such as Field Programmable Gate Arrays (FPGAs). The development of industrial systems can benefit from this new technology by utilizing these cheap components. In this thesis, examples of video processing algorithms suitable for pre-processing of digital video applicable for both industrial and media usage will be shown. In addition a methodology supporting the designer in implementing memory architectures suitable for such algorithms is presented. In this thesis two video processing algorithms are presented and described in detail. The common denominator is their utilization of data from temporally adjacent frames in order to be effective, in terms of compression efficiency, and to produce an attractive result for the viewer. However, from the aspect of quality improvement, considerations have to be taken into account in order to enable an actual hardware implementation. Utilizing data from temporally adjacent frames in a real-time data stream is a non-trivial task. From the algorithm designer’s view the data dependencies and memory requirements are not in focus, but for the hardware designer they are. Having the right data available at the right time is the only consideration in order to have a functional system. Present day algorithm and hardware development methods and architectures do not converge into a common design flow, even though this has been attempted. The gap between the algorithm designer and his/her hardware counterpart has to be bridged in order to obtain an efficient and rapid implementation. Methodologies that abstract and reduce the amount of time spent on implementing memory architectures for video processing applications are required. The buffering requirements are often too complex to analyze manually in order to efficiently utilize the resources available in FPGAs. In this thesis a method for the synthesis and implementation of memory architectures for real-time video processing systems, IMapper, is presented. The architecture supports the implementation of spatio- and temporal video processing algorithms and utilizes methodologies for global optimization of on-fabric available memory resources for FPGAs. This methodology provides an efficient and flexible implementation environment and also offers the benefits of the global optimizations it utilizes

Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet , 2006. , p. 116
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 13
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-8881ISBN: 91-85317-36-5 (print)OAI: oai:DiVA.org:miun-8881DiVA, id: diva2:216072
Public defence
2006-12-15, Sundsvall, 08:30 (English)
Opponent
Supervisors
Available from: 2009-05-06 Created: 2009-05-06 Last updated: 2009-07-13Bibliographically approved
List of papers
1. Spatio-Temporal Noise Reduction algorithm targeting Real-Time Video Processing
Open this publication in new window or tab >>Spatio-Temporal Noise Reduction algorithm targeting Real-Time Video Processing
2000 (English)In: Proceedings of IEEE International Symposium on Information Theory and Its Applications 2000, 2000Conference paper, Published paper (Refereed)
Keywords
Noise reduction Real-Time Video
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-1651 (URN)272 (Local ID)272 (Archive number)272 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-08-28Bibliographically approved
2. Cubic Vector Median Filter for Noise Reduction and Improvement of Compression Efficiency
Open this publication in new window or tab >>Cubic Vector Median Filter for Noise Reduction and Improvement of Compression Efficiency
2004 (English)In: IWSSIP'04 : international workshop on systems, signals and image processing :   ( Poznan, 13-15 September 2004 ), Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering , 2004Conference paper, Published paper (Refereed)
Abstract [en]

Encoding of image sequences is today a standard task for computers and home entertainment systems. The input material is often of shifting quality, i.e. corrupted by noise in various ways. In order to store the information in an effective way some kind of compression has to be applied. When video compression is applied on an image sequence, the result is sub optimal due to the introduced noise variations. This paper presents a new cubic median filter suitable for pre-processing of noise contaminated video sequences. The presented approach reduces the bit usage for MPEG-2 encoding with up to 62% for impulse noise impaired sequences and 38% for the corresponding Gaussian.

Place, publisher, year, edition, pages
Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering, 2004
Keywords
Median filter Cubic Compression
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2356 (URN)1974 (Local ID)1974 (Archive number)1974 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2012-02-16Bibliographically approved
3. Comparison of Noise Reduction and MPEG-2 Compression Efficiency for Pre-Processing Video Filters
Open this publication in new window or tab >>Comparison of Noise Reduction and MPEG-2 Compression Efficiency for Pre-Processing Video Filters
2004 (English)In: IWSSIP'04 : international workshop on systems, signals and image processing :   ( Poznan, 13-15 September 2004 ), Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering , 2004Conference paper, Published paper (Refereed)
Abstract [en]

Video information that is input in digital video recorders or distributed over the Internet comes in various different qualities. One possibility to improve the video quality and also to improve the efficiency of the video encoder is to use different types of spatial or temporal video filters. This paper presents a comparison of the noise reduction efficiency for three different video filters. Additionally, the improvement of MPEG-2 encoding efficiency is compared. The results provide an efficiency function that can be used to select an appropriate filter type for a special situation.

Place, publisher, year, edition, pages
Poznan, Poland: Polish Society for Theoretical and Applied Electrical Engineering, 2004
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2380 (URN)1975 (Local ID)1975 (Archive number)1975 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2012-02-16Bibliographically approved
4. Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
Open this publication in new window or tab >>Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
2007 (English)In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, Vol. 2007, article id 75368Article in journal (Refereed) Published
Abstract [en]

This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

Keywords
Embedded systems, Video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3879 (URN)10.1155/2007/75368 (DOI)2-s2.0-33846809178 (Scopus ID)4203 (Local ID)4203 (Archive number)4203 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
5. A Comparison between Local and Global Memory Allocation for FPGA Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>A Comparison between Local and Global Memory Allocation for FPGA Implementation of Real-Time Video Processing Systems
2004 (English)In: Proceedings of the IEEE International Conference on Signals and Electronic Systems, 2004Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a comparison of local and global memory allocation for implementation of real-time video processing systems on FPGAs. The paper compares new methods to perform memory allocation using single and dual port block RAMs to memory allocation methods found in the literature. This investigation shows that the use of global allocation can reduce the memory size by up to 75 % for the two presented video processing systems.

Keywords
FPGA, real-time video, memory allocation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2379 (URN)1973 (Local ID)1973 (Archive number)1973 (OAI)
Available from: 2008-09-30 Created: 2008-12-16Bibliographically approved
6. A Generalized Architecture for Hardware Synthesis of Spatio-Temporal Memory Models for Image Processing Systems
Open this publication in new window or tab >>A Generalized Architecture for Hardware Synthesis of Spatio-Temporal Memory Models for Image Processing Systems
2005 (English)In: IWSSIP 2005 - Proceedings of the 12th International Worshop on Systems, Signals & Image Processing, InderScience Publishers, 2005, p. 361-365Conference paper, Published paper (Refereed)
Abstract [en]

This paper presents a generalized architecture for the synthesis of application specific memory architectures for real-time image processing systems. The memory generation presented in this paper can handle both spatial and spatio-temporal memory models. The results show that the architecture efficiently solves the problems related to memory accesses for most of the available video image processing filters available at present.

Place, publisher, year, edition, pages
InderScience Publishers, 2005
Keywords
FPGA, Image processing, Memory Architecture
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3254 (URN)000234244500072 ()2-s2.0-32544451657 (Scopus ID)3214 (Local ID)0-907776-20-5 (ISBN)3214 (Archive number)3214 (OAI)
Conference
IWSSIP 2005 - 12th International Workshop on Systems, Signals and Image Processing(SSIP-SPI, 2005); Chalkida; Greece; 22 September 2005 through 24 September 2005; Code 66610
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2016-09-27Bibliographically approved
7. Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
Open this publication in new window or tab >>Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
2007 (English)In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, Vol. 2007, article id 75368Article in journal (Refereed) Published
Abstract [en]

This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

Keywords
Embedded systems, Video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3879 (URN)10.1155/2007/75368 (DOI)2-s2.0-33846809178 (Scopus ID)4203 (Local ID)4203 (Archive number)4203 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
8. VIPS: Video Image Processing In a Second
Open this publication in new window or tab >>VIPS: Video Image Processing In a Second
2006 (English)Conference paper, Published paper (Refereed)
Keywords
Pre-processing, Video
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3880 (URN)4202 (Local ID)4202 (Archive number)4202 (OAI)
Available from: 2008-09-30 Created: 2008-09-30Bibliographically approved

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