A new asymmetrical cascaded multilevel inverter with reduced number of componentsShow others and affiliations
2018 (English)In: Proceedings: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 4429-4433, article id 8591578Conference paper, Published paper (Refereed)
Abstract [en]
Multilevel inverters (MLIs) are known as one of the most widely used power converters in power electronic fields. This study proposes a new voltage source inverter (VSI) for MLI with reduced number of components. The recommended MLI is implemented with 8 DC links and 18 switches, which generates 33 output voltage levels in asymmetric source configuration. All voltage levels (positive, negative and zero) are synthesized at the output terminals without any additional circuit. Cascaded connection of the topology is also proposed. Compared with other conventional and recently invented topologies, it uses less number of components. The accuracy performance of the suggested MLI in synthesizing the positive, negative and also zero voltage levels is verified over the simulation results (MATLAB/SIMULINK software) on a 33- level inverter.
Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018. p. 4429-4433, article id 8591578
Keywords [en]
Asymmetric source configuration, Cascaded multilevel inverter
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-35829DOI: 10.1109/IECON.2018.8591578ISI: 000505811104057Scopus ID: 2-s2.0-85061527063ISBN: 9781509066841 (electronic)OAI: oai:DiVA.org:miun-35829DiVA, id: diva2:1297365
Conference
44th Annual Conference of the IEEE Industrial Electronics Society, IECON 2018, Washington DC, United States, 20 October 2018 through 23 October 2018
2019-03-192019-03-192020-02-19Bibliographically approved