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Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Sensible Things that Communicate, STC)ORCID iD: 0000-0002-3429-273X
2009 (English)Doctoral thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance.

Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ. , 2009. , p. 180
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 66
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-7697ISBN: 978-91-86073-26-8 (print)OAI: oai:DiVA.org:miun-7697DiVA, id: diva2:128002
Public defence
2009-01-07, O102, Mittuniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things that Communicate
Note
Electronics design divisionAvailable from: 2008-12-19 Created: 2008-12-11 Last updated: 2011-02-06Bibliographically approved
List of papers
1. Embedded FPGA memory requirements for real-time video processing applications
Open this publication in new window or tab >>Embedded FPGA memory requirements for real-time video processing applications
2005 (English)In: 23rd NORCHIP Conference 2005, IEEE conference proceedings, 2005, p. 206-209, article id 1597025Conference paper, Published paper (Refereed)
Abstract [en]

FPGAs show interesting properties for real-time implementation of video processing systems. An important feature is the available on-chip RAM blocks embedded on the FPGAs. This paper presents an analysis of the current and future requirements of video processing systems put on these embedded memory resources. The analysis is performed such that a set of video processing systems are allocated onto different existing and extrapolated FPGA architectures. The analysis shows that FPGAs should support multiple memory sizes to take full advantage of the architecture. These results are valuable for both designers of systems and for planning the development of new FPGA architectures

Place, publisher, year, edition, pages
IEEE conference proceedings, 2005
Keywords
embedded RAM, FPGA, video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3332 (URN)10.1109/NORCHP.2005.1597025 (DOI)2-s2.0-33847233912 (Scopus ID)3287 (Local ID)1-4244-0064-3 (ISBN)3287 (Archive number)3287 (OAI)
Conference
23rd NORCHIP Conference 2005; Oulu; Finland; 21 November 2005 through 22 November 2005
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-30 Last updated: 2016-10-04Bibliographically approved
2. Ram allocation algorithm for video processing applications on FPGA
Open this publication in new window or tab >>Ram allocation algorithm for video processing applications on FPGA
2006 (English)In: Journal of Circuits, Systems and Computers, ISSN 0218-1266, Vol. 15, no 5, p. 679-699Article in journal (Refereed) Published
Abstract [en]

This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.

Keywords
Allocation algorithm, FPGA, Global block RAM, Real-time, Video processing system
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3849 (URN)10.1142/S0218126606003295 (DOI)000244309500003 ()2-s2.0-33846524776 (Scopus ID)4105 (Local ID)4105 (Archive number)4105 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2017-12-12Bibliographically approved
3. Power-aware automatic constraint generation for FPGA based real-time video processing systems
Open this publication in new window or tab >>Power-aware automatic constraint generation for FPGA based real-time video processing systems
2007 (English)In: 25th Norchip Conference, NORCHIP, New York: IEEE conference proceedings, 2007, p. 124-128Conference paper, Published paper (Refereed)
Abstract [en]

The introduction of embedded DSP blocks and embedded memory has made FPGAs an attractive architecture for implementation of real-time video processing systems. The big bottle neck of the FPGA compared to other programmable architectures is the complex programming model. This paper presents an automatic generation of placement and routing constraints for FPGA implementation of real-time video processing systems as one step to automate the programming model. The constraint generator targets lower power consumption, better resource utilization and reduced development time. Results show that a 28 % reduction in dynamic power can be achieved using the proposed approach over traditional logic to memory mapping.

Place, publisher, year, edition, pages
New York: IEEE conference proceedings, 2007
Keywords
FPGA
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-4375 (URN)10.1109/NORCHP.2007.4481054 (DOI)000257311000029 ()2-s2.0-50249090387 (Scopus ID)5278 (Local ID)978-1-4244-1516-8 (ISBN)5278 (Archive number)5278 (OAI)
Conference
25th Norchip Conference, Nov 19-20, 2007, Aalborg, Denmark
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2017-10-18Bibliographically approved
4. Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
2005 (English)In: Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, IEEE conference proceedings, 2005, p. 136-141, article id 1515712Conference paper, Published paper (Refereed)
Abstract [en]

FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2005
Keywords
Real-time Image Processing, FPGA, Memory Allocation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3314 (URN)10.1109/FPL.2005.1515712 (DOI)2-s2.0-33746903967 (Scopus ID)3226 (Local ID)0-7803-9362-7 (ISBN)3226 (Archive number)3226 (OAI)
Conference
2005 International Conference on Field Programmable Logic and Applications, FPL; Tampere; Finland; 24 August 2005 through 26 August 2005
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-12-19 Last updated: 2016-09-29Bibliographically approved
5. Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
Open this publication in new window or tab >>Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
2007 (English)In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, Vol. 2007, article id 75368Article in journal (Refereed) Published
Abstract [en]

This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

Keywords
Embedded systems, Video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3879 (URN)10.1155/2007/75368 (DOI)2-s2.0-33846809178 (Scopus ID)4203 (Local ID)4203 (Archive number)4203 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
6. C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
Open this publication in new window or tab >>C++ based System Synthesis of Real-Time Video Processing Systems targeting FPGA Implementation
2006 (English)In: Proceedings of the FPGA World Conference 2006, 2006Conference paper, Published paper (Refereed)
Abstract [en]

Implementing real-time video processing systems put high requirements on computation and memory performance. FPGAs have shown to be an effective implementation architecture for these systems. However, the hardware based design flow for FPGAs make the implementation task complex. The system synthesis tool presented in this paper reduces this design complexity. The synthesis is done from a SystemC based coarse grain data flow graph that captures the video processing system. The data flow graph is optimized and mapped onto an FPGA. The results from real-life video processing systems clearly show that the presented tool produces effective implementations.

Keywords
FPGA, real-time, video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3905 (URN)4266 (Local ID)4266 (Archive number)4266 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2011-02-06Bibliographically approved
7. Architecture driven memory allocation for FPGA Based Real-Time Video Processing Systems
Open this publication in new window or tab >>Architecture driven memory allocation for FPGA Based Real-Time Video Processing Systems
2011 (English)In: Proceedings of the 2011 7th Southern Conference on Programmable Logic, SPL 2011 2011, Article number 5782639, IEEE conference proceedings, 2011, p. 143-148Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present an approach that uses information about the FPGA architecture to achieve optimized allocation of embedded memory in real-time video processing system. A cost function defined in terms of required memory sizes, available block- and distributed-RAM resources is used to motivate the allocation decision. This work is a high-level exploration that generates VHDL RTL modules and synthesis constraint files to specify memory allocation. Results show that the proposed approach achieves appreciable reduction in block RAM usage over previous logic to memory mapping approach at negligible increase in logic usage

Place, publisher, year, edition, pages
IEEE conference proceedings, 2011
Keywords
Allocation decision; Block rams; Embedded memories; FPGA architectures; Memory mapping; Memory size; Optimized allocation; Real-time video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7834 (URN)10.1109/SPL.2011.5782639 (DOI)2-s2.0-79959299691 (Scopus ID)STC (Local ID)978-142448848-3 (ISBN)STC (Archive number)STC (OAI)
Conference
2011 7th Southern Conference on Programmable Logic, SPL 2011; Cordoba; 13 April 2011 through 15 April 2011; Category number CFP1121B-ART; Code 85185
Available from: 2008-12-19 Created: 2008-12-19 Last updated: 2016-10-19Bibliographically approved

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Lawal, Najeem

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Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
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  • en-GB
  • en-US
  • fi-FI
  • nn-NO
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Output format
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