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Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media.ORCID iD: 0000-0002-3429-273X
2006 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance.

Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

Place, publisher, year, edition, pages
Sundvall: Mid Sweden Univ. , 2006. , p. 114
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 14
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-7696ISBN: 91-85317-30-6 (print)OAI: oai:DiVA.org:miun-7696DiVA, id: diva2:128000
Presentation
2006-11-22, M102, MittUniversitetet, Sundsvall, 10:30 (English)
Opponent
Supervisors
Projects
Sensible Things That Communicate
Available from: 2008-12-19 Created: 2008-12-11 Last updated: 2009-02-13Bibliographically approved
List of papers
1. Embedded FPGA memory requirements for real-time video processing applications
Open this publication in new window or tab >>Embedded FPGA memory requirements for real-time video processing applications
2005 (English)In: 23rd NORCHIP Conference 2005, IEEE conference proceedings, 2005, p. 206-209, article id 1597025Conference paper, Published paper (Refereed)
Abstract [en]

FPGAs show interesting properties for real-time implementation of video processing systems. An important feature is the available on-chip RAM blocks embedded on the FPGAs. This paper presents an analysis of the current and future requirements of video processing systems put on these embedded memory resources. The analysis is performed such that a set of video processing systems are allocated onto different existing and extrapolated FPGA architectures. The analysis shows that FPGAs should support multiple memory sizes to take full advantage of the architecture. These results are valuable for both designers of systems and for planning the development of new FPGA architectures

Place, publisher, year, edition, pages
IEEE conference proceedings, 2005
Keyword
embedded RAM, FPGA, video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3332 (URN)10.1109/NORCHP.2005.1597025 (DOI)2-s2.0-33847233912 (Scopus ID)3287 (Local ID)1-4244-0064-3 (ISBN)3287 (Archive number)3287 (OAI)
Conference
23rd NORCHIP Conference 2005; Oulu; Finland; 21 November 2005 through 22 November 2005
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-30 Last updated: 2016-10-04Bibliographically approved
2. Ram allocation algorithm for video processing applications on FPGA
Open this publication in new window or tab >>Ram allocation algorithm for video processing applications on FPGA
2006 (English)In: Journal of Circuits, Systems and Computers, ISSN 0218-1266, Vol. 15, no 5, p. 679-699Article in journal (Refereed) Published
Abstract [en]

This paper presents an algorithm for the allocation of on-chip FPGA Block RAMs for the implementation of Real-Time Video Processing Systems. The effectiveness of the algorithm is shown through the implementation of realistic image processing systems. The algorithm, which is based on a heuristic, seeks the most cost-effective way of allocating memory objects to the FPGA Block RAMs. The experimental results obtained, show that this algorithm generates results which are close to the theoretical optimum for most design cases.

Keyword
Allocation algorithm, FPGA, Global block RAM, Real-time, Video processing system
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3849 (URN)10.1142/S0218126606003295 (DOI)000244309500003 ()2-s2.0-33846524776 (Scopus ID)4105 (Local ID)4105 (Archive number)4105 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2009-07-29 Last updated: 2017-12-12Bibliographically approved
3. Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
Open this publication in new window or tab >>Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
2005 (English)In: Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, IEEE conference proceedings, 2005, p. 136-141, article id 1515712Conference paper, Published paper (Refereed)
Abstract [en]

FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2005
Keyword
Real-time Image Processing, FPGA, Memory Allocation
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3314 (URN)10.1109/FPL.2005.1515712 (DOI)2-s2.0-33746903967 (Scopus ID)3226 (Local ID)0-7803-9362-7 (ISBN)3226 (Archive number)3226 (OAI)
Conference
2005 International Conference on Field Programmable Logic and Applications, FPL; Tampere; Finland; 24 August 2005 through 26 August 2005
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-12-19 Last updated: 2016-09-29Bibliographically approved
4. Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
Open this publication in new window or tab >>Automatic Generation of Spatial and Temporal Memory Architectures for Embedded Video Processing Systems
2007 (English)In: EURASIP Journal on Embedded Systems, ISSN 1687-3955, E-ISSN 1687-3963, Vol. 2007, article id 75368Article in journal (Refereed) Published
Abstract [en]

This paper presents a tool for automatic generation of the memory management implementation for spatial and temporal real-time video processing systems targeting field programmable gate arrays (FPGAs). The generator creates all the necessary memory and control functionality for a functional spatio-temporal video processing system. The required memory architecture is automatically optimized and mapped to the FPGAs' memory resources thus producing an efficient implementation in terms of used internal resources. The results in this paper show that the tool is able to efficiently and automatically generate all required memory management modules for both spatial and temporal real-time video processing systems.

Keyword
Embedded systems, Video processing
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3879 (URN)10.1155/2007/75368 (DOI)2-s2.0-33846809178 (Scopus ID)4203 (Local ID)4203 (Archive number)4203 (OAI)
Projects
STC - Sensible Things that Communicate
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
5. Comparison of FPGA and DSP performances in neighbourhood oriented real-time video processing
Open this publication in new window or tab >>Comparison of FPGA and DSP performances in neighbourhood oriented real-time video processing
(English)Manuscript (Other academic)
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7835 (URN)
Note
Submitted to: Transactions of VLSI Systems Special Section on Configurable Computing SystemsAvailable from: 2008-12-19 Created: 2008-12-19 Last updated: 2010-01-14Bibliographically approved

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