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Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply
Mid Sweden University, Faculty of Science, Technology and Media, Department of Information Technology and Media. (Electronics design division)
Department of Informatics, University of Oslo.
Responsible organisation
2007 (English)In: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Berlin: Springer, 2007, p. 536-546Conference paper, Published paper (Refereed)
Abstract [en]

To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

Place, publisher, year, edition, pages
Berlin: Springer, 2007. p. 536-546
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 4644/2007
Keywords [en]
low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-5929DOI: 10.1007/978-3-540-74442-9_52ISI: 000249581300052Scopus ID: 2-s2.0-37849004999Local ID: 4991ISBN: 978-3-540-74441-2 (print)OAI: oai:DiVA.org:miun-5929DiVA, id: diva2:30962
Conference
PATMOS - 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep 03-05, 2007, Gothenburg, Sweden
Projects
STC - Sensible Things that CommunicateAvailable from: 2009-01-07 Created: 2009-01-07 Last updated: 2016-09-26Bibliographically approved
In thesis
1. Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
Open this publication in new window or tab >>Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2008. p. 129
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 54
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7567 (URN)978-91-85317-97-4 (ISBN)
Public defence
(English)
Supervisors
Available from: 2008-12-10 Created: 2008-12-10 Last updated: 2011-02-06Bibliographically approved

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Alfredsson, Jon

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CiteExportLink to record
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Citation style
  • apa
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  • vancouver
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Language
  • de-DE
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  • fi-FI
  • nn-NO
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  • Other locale
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Output format
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  • asciidoc
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