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D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier. (Electronics design division)
Department of Informatics, University of Oslo.
Ansvarlig organisasjon
2007 (engelsk)Inngår i: 2007 NORCHIP, IEEE conference proceedings, 2007, s. 146-149Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

sted, utgiver, år, opplag, sider
IEEE conference proceedings, 2007. s. 146-149
Emneord [en]
Subthreshold, Floating-gate, digital, latch, low power
HSV kategori
Identifikatorer
URN: urn:nbn:se:miun:diva-4451ISI: 000257311000034Scopus ID: 2-s2.0-50249139531Lokal ID: 5436ISBN: 978-1-4244-1516-8 (tryckt)OAI: oai:DiVA.org:miun-4451DiVA, id: diva2:29483
Konferanse
25th Norchip Conference, Nov 19-20, 2007, Aalborg, Denmark
Prosjekter
STC - Sensible Things that CommunicateTilgjengelig fra: 2009-01-07 Laget: 2009-01-07 Sist oppdatert: 2017-10-18bibliografisk kontrollert
Inngår i avhandling
1. Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
Åpne denne publikasjonen i ny fane eller vindu >>Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
2008 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
sted, utgiver, år, opplag, sider
Sundsvall: Mid Sweden University, 2008. s. 129
Serie
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 54
HSV kategori
Identifikatorer
urn:nbn:se:miun:diva-7567 (URN)978-91-85317-97-4 (ISBN)
Disputas
(engelsk)
Veileder
Tilgjengelig fra: 2008-12-10 Laget: 2008-12-10 Sist oppdatert: 2011-02-06bibliografisk kontrollert

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