Finite state machine (FSM) partitioning proves effective for power optimization. In this paper we propose a design model based on mixed synchronous/asynchronous state memory that results in implementations with low power dissipation and low area overhead for partitioned FSM.s. The state memory here is composed of the synchronous local state memory and asynchronous global state memory, where the former is used to distinguish the states inside a sub-FSM, and the latter is responsible for controlling sub-FSM communication. The input and output behaviour of the decomposed FSM is cycle by cycle equivalent to the undecomposed synchronous FSM. Together with clock gating technique, substantial power reduction can be demonstrated.

An efficient way to obtain finite-state machines (FSMs) with low-power consumption is to partition the machine into two or more sub-FSMs and then use dynamic power management where all sub-FSMs not active are shut down, with the effect of reducing dynamic power dissipation. Thus, FSM partitioning algorithms and register-transfer-level power estimation functions are the main focus of the paper as these are key issues in the design of a computer-aided design tool for synthesis of low-power partitioned FSMs. An implementation architecture is targeted, which is based on both synchronous and asynchronous state memory elements that enable larger power reductions than fully synchronous architectures do. Power reductions of up to 77 have been achieved at a cost of an 18 increase in area.

Partitioned finite state machine (FSM) architectures in general enable low-power implementations and it has been shown that for these architectures, state memory based on both synchronous and asynchronous storage elements gives lower power consumption compared to their fully synchronous counterparts. In this paper we present state encoding techniques for a partitioned FSM architecture based on mixed synchronous/asynchronous state memory. The state memory, in this case, is composed of a synchronous local state memory and an asynchronous global state memory. The local state memory uses synchronous storage elements and is shared by all sub-FSMs. The global state memory operates asynchronously and is responsible for handling the interaction between sub-FSMs. Even though the partitioned FSM contains the asynchronous mechanism, its input/output behaviour is still cycle by cycle equivalent to the original monolithic synchronous FSM. In this paper, we discuss the low-power state encoding method for the implementation of partitioned FSM with mixed synchronous/asynchronous state memory. For the local state assignment a, what we call, state-bundling procedure is presented to enable states residing in different sub-FSMs to share the same state codes. Based on state-bundles, two state encoding techniques, in which one is the employment of binary encoding and the other is the further optimization for low power, are compared.

Finite State Machine (FSM) partitioning together with a Dynamic Power Management (DPM) scheme is an efficient method for low-power FSM design. Taking both power and area into account at an early stage of FSM partitioning is important for choosing an efficient partitioning in terms of both power and area. There are certain FSMs that a partitioning solution with the lowest power has a big area overhead. For them, exploring the area-power trade-off is especially helpful for finding an alternative partitioning with slightly higher power consumption but much lower area. In this paper, we explore the area-power trade-off in FSM partitioning and propose the area cost functions that are verified by correlation coefficient. A relative comparison of the estimated area cost among the partitioning solutions gives the user more freedom to trade power for area. Since the gate-level implementation is unknown, the area constraint should be given in relative terms, not as the specific percentage of area increase allowed

Benchmarking is a common way to evaluate the effectiveness of finite state machine (FSM) low-power methodologies. The serious problem in the existing standard benchmarks is that power-related characteristics are not provided, and therefore these benchmarks are not complete for reliable evaluation and comparison of low-power methods and tools. To address this problem, this paper introduces the coefficient of variation, which is very useful for quantitative analysis of power-related features of an FSM, and for indicating the power optimization opportunity of the corresponding circuit. Based on the coefficient of variation, input-sensitivity analysis of the whole standard benchmark set is conducted. It reveals that the benchmark set is input-data dependant, and the set is insufficient for low-power FSM researches due to the limited coverage of power-related characteristics.