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Membrane Covered Electrically Isolated Through-Wafer Via Holes
Uppsala universitet, Institutionen för materialvetenskap.
Uppsala universitet, Institutionen för materialvetenskap.
Uppsala universitet, Institutionen för materialvetenskap.ORCID iD: 0000-0003-2352-9006
2001 (English)In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 11, no 4, p. 344-347Article in journal (Refereed) Published
Abstract [en]

An electrically isolated through-wafer via hole, covered by a membrane, has been realized by standard integrated circuits processes together with deep silicon etching. The deep silicon etching was performed by the Bosch silicon etch process in a Plasma-Therm etch system. The via structures were made in double-sided polished 300 µm thick silicon wafers and had widths down to 20 µm, which correspond to an aspect ratio of 15. The fact that the via structures are electrically isolated makes them a suitable start-point to realize interconnections through a wafer. Furthermore, the application field of the via structure is broadened by the flexibility in the design of the structure, which makes it possible to apply an almost arbitrary membrane material onto the via structure at the end of the process.

Place, publisher, year, edition, pages
2001. Vol. 11, no 4, p. 344-347
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
URN: urn:nbn:se:miun:diva-31604DOI: 10.1088/0960-1317/11/4/310OAI: oai:DiVA.org:miun-31604DiVA, id: diva2:1140933
Available from: 2007-02-27 Created: 2017-09-13 Last updated: 2017-09-13Bibliographically approved

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Hedlund, Christer

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