miun.sePublikationer
Ändra sökning
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf
Design of a Parallel A/D-converter System on PCB - For High-Speed Sampling and Timing Error Correction: Examensarbete - Linköpings universitet
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier.
Ansvarig organisation
2002 (Engelska)Övrigt (Övrigt vetenskapligt)
Abstract [en]

The goals for most of today´s receiver system are sampling at high-speed, with high resolution and with as few errors as possible. This master thesis describes the design of a high-speed sampling system with �state-of-the-art� components available on the market. The system is designed with a parallel Analog-to-digital converter (ADC) architecture, also called time interleaving. It aims to increase the sampling speed of the system. The system described in this report uses four 12-bits ADCs in parallel. Each ADC can sample at 125 MHz and the total sampling speed will then theoretically become 500 Ms/s. The system has been implemented and manufactured on a printed circuit board (PCB). Up to four boards can be connected in parallel to get 2 Gs/s theoretically. In an approach to increase the systems performance even further, a timing error estimation algorithm will be used on the sampled data. This algorithm estimates the timing errors that occur when sampling with non-uniform time interval between samples. After the estimations, the sampling clocks can be adjusted to correct the errors. This thesis is concerning some ADC theory, system design and PCB implementation. It also describes how to test and measure the system�s performance. No measurement results are presented in this thesis because measurements will be done after this project. The last part of the thesis discusses future improvements to achieve even higher performance.

Ort, förlag, år, sidor
2002.
Nyckelord [en]
Analog-to-digital converter, ADC, A/D, sampling system, high speed, timing error, estimation algorithm, time interleaving, parallel architecture, PCB design, conveter, undersampling
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
URN: urn:nbn:se:miun:diva-5294Lokalt ID: 550OAI: oai:DiVA.org:miun-5294DiVA, id: diva2:30326
Tillgänglig från: 2008-09-30 Skapad: 2009-01-07Bibliografiskt granskad

Open Access i DiVA

Fulltext saknas i DiVA

Personposter BETA

Alfredsson, Jon

Sök vidare i DiVA

Av författaren/redaktören
Alfredsson, Jon
Av organisationen
Institutionen för informationsteknologi och medier
Elektroteknik och elektronik

Sök vidare utanför DiVA

GoogleGoogle Scholar

urn-nbn

Altmetricpoäng

urn-nbn
Totalt: 311 träffar
RefereraExporteraLänk till posten
Permanent länk

Direktlänk
Referera
Referensformat
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Annat format
Fler format
Språk
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Annat språk
Fler språk
Utmatningsformat
  • html
  • text
  • asciidoc
  • rtf