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Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier. (Electronics design division)
Department of Informatics, University of Oslo.
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier. (STC)
Ansvarig organisation
2007 (Engelska)Ingår i: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, IEEE conference proceedings, 2007, s. 314-317Konferensbidrag, Publicerat paper (Refereegranskat)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

Ort, förlag, år, upplaga, sidor
IEEE conference proceedings, 2007. s. 314-317
Serie
International Conference on VLSI Design, Proceedings, ISSN 1063-9667
Nyckelord [en]
Low power, Digital CMOS, Floating-gate
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
URN: urn:nbn:se:miun:diva-3900DOI: 10.1109/VLSID.2007.143ISI: 000245425300045Scopus ID: 2-s2.0-48349148523Lokalt ID: 4258ISBN: 978-0-7695-2762-8 (tryckt)OAI: oai:DiVA.org:miun-3900DiVA, id: diva2:28932
Konferens
20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems, jan 06-10, 2007, Bangalore, india
Projekt
STC - Sensible Things that CommunicateTillgänglig från: 2009-01-07 Skapad: 2009-01-07 Senast uppdaterad: 2017-10-20Bibliografiskt granskad
Ingår i avhandling
1. Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
Öppna denna publikation i ny flik eller fönster >>Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
2008 (Engelska)Doktorsavhandling, sammanläggning (Övrigt vetenskapligt)
Ort, förlag, år, upplaga, sidor
Sundsvall: Mid Sweden University, 2008. s. 129
Serie
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 54
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
urn:nbn:se:miun:diva-7567 (URN)978-91-85317-97-4 (ISBN)
Disputation
(Engelska)
Handledare
Tillgänglig från: 2008-12-10 Skapad: 2008-12-10 Senast uppdaterad: 2011-02-06Bibliografiskt granskad
2. Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
Öppna denna publikation i ny flik eller fönster >>Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
2007 (Engelska)Licentiatavhandling, sammanläggning (Övrigt vetenskapligt)
Abstract [en]

All who is involved in electronic design knows that one of the critical issues

in today’s electronic is the power consumption. Designers are always looking for

new approaches in order to reduce currents while still retain performance.

Floating-gate (FGMOS) circuits have previously been shown to be a promising

technique to improve speed and still keep the power consumption low when

power supply is reduced below subthreshold voltage for the transistors.

In this thesis, the goal is to determine how good floating-gate circuits can be

compared to conventional static CMOS when the circuits are working in

subthreshold. The most interesting performance parameters are speed and power

consumption and specifically the Energy-Delay Product (EDP) that is a

combination of those two. To get a view over how the performance varies and how

good the FGMOS circuits are at their best case, the circuits have been designed and

simulated for best case performance.

The investigation also includes trade-offs with speed and power

consumption for better performance, how to select floating-gate capacitances, how

a large circuit fan-in will affect performance and also the influence of different

kinds of refresh circuits.

The first simulations of the FGMOS circuits in a 0.13 μm process have

several interesting results. First of all, in the best case it is shown that FGMOS has

potential to achieve up to 260 times in better EDP-performance compared to CMOS

at 150 mV power supply. Continuing with simulations of FGMOS capacitances

shows that minimum floating-gate capacitance can be as small as 400 fF and more

realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

capacitances included). Other aspects of FGMOS design have been to look at how

refresh circuits will affect performance (semi-floating-gate circuits) and how a

larger fan-in will change noise margin and EDP. It turns out that refresh circuits

with the same transistor size does not give a noticeable change in performance

while an increase of 8 times in size will give between 5 and 10 times wors EDP.

When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

150 mV.

Finally, it should be kept in mind that tuning the performance of FGMOS

circuits with trade-offs and by changing the floating-gate voltages to achieve

results like the ones stated above will also always affect the noise margins, NM, of

the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

fabricated circuit with that NM may not be as functional as simulations suggests.

The probability to design functional FGMOS circuits in subthreshold does not

seem to be a problem though.

Ort, förlag, år, upplaga, sidor
Sundsvall: Mittuniversitetet, 2007. s. 44
Serie
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 18
Nationell ämneskategori
Elektroteknik och elektronik
Identifikatorer
urn:nbn:se:miun:diva-9333 (URN)91-85317-35-7 (ISBN)
Presentation
(Engelska)
Opponent
Handledare
Tillgänglig från: 2009-07-10 Skapad: 2009-07-10 Senast uppdaterad: 2011-02-06Bibliografiskt granskad

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Alfredsson, JonOelmann, Bengt

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