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Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier. (Electronics design division)ORCID-id: 0000-0002-3429-273X
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier. (Electronics design division, STC)
Mittuniversitetet, Fakulteten för naturvetenskap, teknik och medier, Institutionen för informationsteknologi och medier.
Ansvarlig organisasjon
2005 (engelsk)Inngår i: Proceedings - 2005 International Conference on Field Programmable Logic and Applications, FPL, IEEE conference proceedings, 2005, s. 136-141, artikkel-id 1515712Konferansepaper, Publicerat paper (Fagfellevurdert)
Abstract [en]

FPGA offers the potential of being a reliable, and high-performance reconfigurable platform for the implementation of real-time video processing systems. To utilize the full processing power of FPGA for video processing applications, optimization of memory accesses and the implementation of memory architecture are important issues. This paper presents two approaches, base pointer approach and distributed pointer approach, to implement accesses to on-chip FPGA Block RAMs. A comparison of the experimental results obtained using the two approaches on realistic image processing systems design cases is presented. The results show that compared to the base pointer approach the distributed pointer approach increases the potential processing power of FPGA, as a reconfigurable platform for video processing systems.

sted, utgiver, år, opplag, sider
IEEE conference proceedings, 2005. s. 136-141, artikkel-id 1515712
Emneord [en]
Real-time Image Processing, FPGA, Memory Allocation
HSV kategori
Identifikatorer
URN: urn:nbn:se:miun:diva-3314DOI: 10.1109/FPL.2005.1515712Scopus ID: 2-s2.0-33746903967Lokal ID: 3226ISBN: 0-7803-9362-7 (tryckt)OAI: oai:DiVA.org:miun-3314DiVA, id: diva2:28346
Konferanse
2005 International Conference on Field Programmable Logic and Applications, FPL; Tampere; Finland; 24 August 2005 through 26 August 2005
Prosjekter
STC - Sensible Things that CommunicateTilgjengelig fra: 2008-09-30 Laget: 2008-12-19 Sist oppdatert: 2016-09-29bibliografisk kontrollert
Inngår i avhandling
1. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Åpne denne publikasjonen i ny fane eller vindu >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2006 (engelsk)Licentiatavhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include object recognition, object tracking and surveillance.

Developments in field programmable gate array (FPGA) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operation are currently available optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimal use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) codes for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimal use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

sted, utgiver, år, opplag, sider
Sundvall: Mid Sweden Univ., 2006. s. 114
Serie
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 14
HSV kategori
Identifikatorer
urn:nbn:se:miun:diva-7696 (URN)91-85317-30-6 (ISBN)
Presentation
2006-11-22, M102, MittUniversitetet, Sundsvall, 10:30 (engelsk)
Opponent
Veileder
Prosjekter
Sensible Things That Communicate
Tilgjengelig fra: 2008-12-19 Laget: 2008-12-11 Sist oppdatert: 2009-02-13bibliografisk kontrollert
2. Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
Åpne denne publikasjonen i ny fane eller vindu >>Memory Synthesis for FPGA Implementation of Real-Time Video Processing Systems
2009 (engelsk)Doktoravhandling, med artikler (Annet vitenskapelig)
Abstract [en]

In this thesis, both a method and a tool to enable efficient memory synthesis for real-time video processing systems on field programmable logic array are presented. In real-time video processing system (RTVPS), a set of operations are repetitively performed on every image frame in a video stream. These operations are usually computationally intensive and, depending on the video resolution, can also be very data transfer dominated. These operations, which often require data from several consecutive frames and many rows of data within each frame, must be performed accurately and under real-time constraints as the results greatly affect the accuracy of application. Application domains of these systems include machine vision, object recognition and tracking, visual enhancement and surveillance.

Developments in field programmable gate arrays (FPGAs) have been the motivation for choosing them as the platform for implementing RTVPS. Essential logic resources required in RTVPS operations are currently available and are optimized and embedded in modern FPGAs. One such resource is the embedded memory used for data buffering during real-time video processing. Each data buffer corresponds to a row of pixels in a video frame, which is allocated using a synthesis tool that performs the mapping of buffers to embedded memories. This approach has been investigated and proven to be inefficient. An efficient alternative employing resource sharing and allocation width pipelining will be discussed in this thesis.

A method for the optimised use of these embedded memories and, additionally, a tool supporting automatic generation of hardware descriptions language (HDL) modules for the synthesis of the memories according to the developed method are the main focus of this thesis. This method consists of the memory architecture, allocation and addressing. The central objective of this method is the optimised use of embedded memories in the process of buffering data on-chip for an RVTPS operation. The developed software tool is an environment for generating HDL codes implementing the memory sub-components.

The tool integrates with the Interface and Memory Modelling (IMEM) tools in such a way that the IMEM’s output - the memory requirements of a RTVPS - is imported and processed in order to generate the HDL codes. IMEM is based on the philosophy that the memory requirements of an RTVPS can be modelled and synthesized separately from the development of the core RTVPS algorithm thus freeing the designer to focus on the development of the algorithm while relying on IMEM for the implementation of memory sub-components.

sted, utgiver, år, opplag, sider
Sundvall: Mid Sweden Univ., 2009. s. 180
Serie
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 66
HSV kategori
Identifikatorer
urn:nbn:se:miun:diva-7697 (URN)978-91-86073-26-8 (ISBN)
Disputas
2009-01-07, O102, Mittuniversitetet, Sundsvall, 10:30 (engelsk)
Opponent
Veileder
Prosjekter
Sensible Things that Communicate
Merknad
Electronics design divisionTilgjengelig fra: 2008-12-19 Laget: 2008-12-11 Sist oppdatert: 2011-02-06bibliografisk kontrollert

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