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Samadaei, E., Kaviani, M. & Bertilsson, K. (2019). A 13-levels Module (K-Type) with two DC sources for Multilevel Inverters. IEEE transactions on industrial electronics (1982. Print), 66(7), 5186-5196
Open this publication in new window or tab >>A 13-levels Module (K-Type) with two DC sources for Multilevel Inverters
2019 (English)In: IEEE transactions on industrial electronics (1982. Print), ISSN 0278-0046, E-ISSN 1557-9948, Vol. 66, no 7, p. 5186-5196Article in journal (Refereed) Published
Abstract [en]

This paper presents a new reconfiguration module for asymmetrical multilevel inverters in which the capacitors are used as the DC links to creates the levels for staircase waveforms. This configuration of multilevel converter makes a reduction in DC sources. On the other hand, it is possible to generate 13 levels with lower DC sources. The proposed module of multilevel inverter generates 13 levels with two unequal DC sources (2VDC and 1VDC). It also involves two chargeable capacitors and 14 semiconductor switches. The capacitors are self-charging without any extra circuit. The lower number of components makes it desirable to use in wide range of applications. The module is schematized as two back-to-back T-type inverters and some other switches around it. Also, it can be connected as cascade modular which lead to a modular topology with more voltage levels at higher voltages. The proposed module makes the inherent creation of the negative voltage levels without any additional circuit (such as H-bridge circuit). Nearest level control switching modulation (NLC) scheme is applied to achieve high quality sinusoidal output voltage. Simulations are executed in MATLAB/Simulink and a prototype is implemented in the power electronics laboratory which the simulation and experimental results show a good performance.

Keywords
Asymmetric, capacitors, multilevel inverter, nearest level control switching, power electronics, self-charging
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-34710 (URN)10.1109/TIE.2018.2868325 (DOI)000460663300021 ()2-s2.0-85053154849 (Scopus ID)
Available from: 2018-10-12 Created: 2018-10-12 Last updated: 2019-10-16Bibliographically approved
Vijeh, M., Rezanejad, M., Samadaei, E. & Bertilsson, K. (2019). A General Review of Multilevel Inverters Based on Main Submodules: Structural Point of View. IEEE transactions on power electronics, 34(10), 9479-9502
Open this publication in new window or tab >>A General Review of Multilevel Inverters Based on Main Submodules: Structural Point of View
2019 (English)In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 34, no 10, p. 9479-9502Article in journal (Refereed) Published
Abstract [en]

Multilevel inverters (MLIs) are being used in wide range of power electronics applications. These converters that are attracted a lot of attentions during recent years have different topologies with similar basic concept. This paper presents five main submodules (SMs) that are used as the basic structures of MLIs. The paper reviews the common multilevel inverter topologies with the structural point of view. The topologies are divided to main SMs to show conventional MLIs configuration and future topologies that can be created from the main SMs. The comparative study on topologies is investigated with details. The MLIs are categorized and investigated with due attention to some indexes such as the number of components, the ability to create inherent negative voltage, working in regeneration mode and using single DC source.

Keywords
Asymmetric, multilevel inverter (MLI), power electronics, symmetric
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-35505 (URN)10.1109/TPEL.2018.2890649 (DOI)000474581900014 ()2-s2.0-85063804140 (Scopus ID)
Available from: 2019-01-23 Created: 2019-01-23 Last updated: 2019-10-16Bibliographically approved
Saeedian, M., Pouresmaeil, E., Samadaei, E., Godinho Rodrigues, E. M., Godina, R. & Marzband, M. (2019). An innovative dual-boost nine-level inverter with low-voltage rating switches. Energies, 12(2), Article ID 207.
Open this publication in new window or tab >>An innovative dual-boost nine-level inverter with low-voltage rating switches
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2019 (English)In: Energies, ISSN 1996-1073, E-ISSN 1996-1073, Vol. 12, no 2, article id 207Article in journal (Refereed) Published
Abstract [en]

This article presents an innovative switched-capacitor based nine-level inverter employing single DC input for renewable and sustainable energy applications. The proposed configuration generates a step-up bipolar output voltage without end-side H-bridge, and the employed capacitors are charged in a self-balancing form. Applying low-voltage rated switches is another merit of the proposed inverter, which leads to extensive reduction in total standing voltage. Thereby, switching losses as well as inverter cost are reduced proportionally. Furthermore, the comparative analysis against other state-of-the-art inverters depicts that the number of required power electronic devices and implementation cost is reduced in the proposed structure. The working principle of the proposed circuit along with its efficiency calculations and thermal modeling are elaborated in detail. In the end, simulations and experimental tests are conducted to validate the flawless performance of the proposed nine-level topology in power systems.

Keywords
Improved switched-capacitor module, Multi carrier based modulation, Multilevel inverter, Power conversion
Identifiers
urn:nbn:se:miun:diva-35818 (URN)10.3390/en12020207 (DOI)000459743700008 ()2-s2.0-85060519399 (Scopus ID)
Available from: 2019-03-19 Created: 2019-03-19 Last updated: 2019-03-25Bibliographically approved
Vijeh, M., Samadaei, E., Rezanejad, M., Vahedi, H. & Al-Haddad, K. (2018). A new asymmetrical cascaded multilevel inverter with reduced number of components. In: Proceedings: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society. Paper presented at 44th Annual Conference of the IEEE Industrial Electronics Society, IECON 2018, Washington DC, United States, 20 October 2018 through 23 October 2018 (pp. 4429-4433). Institute of Electrical and Electronics Engineers (IEEE), Article ID 8591578.
Open this publication in new window or tab >>A new asymmetrical cascaded multilevel inverter with reduced number of components
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2018 (English)In: Proceedings: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 4429-4433, article id 8591578Conference paper, Published paper (Refereed)
Abstract [en]

Multilevel inverters (MLIs) are known as one of the most widely used power converters in power electronic fields. This study proposes a new voltage source inverter (VSI) for MLI with reduced number of components. The recommended MLI is implemented with 8 DC links and 18 switches, which generates 33 output voltage levels in asymmetric source configuration. All voltage levels (positive, negative and zero) are synthesized at the output terminals without any additional circuit. Cascaded connection of the topology is also proposed. Compared with other conventional and recently invented topologies, it uses less number of components. The accuracy performance of the suggested MLI in synthesizing the positive, negative and also zero voltage levels is verified over the simulation results (MATLAB/SIMULINK software) on a 33- level inverter. 

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2018
Keywords
Asymmetric source configuration, Cascaded multilevel inverter
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-35829 (URN)10.1109/IECON.2018.8591578 (DOI)2-s2.0-85061527063 (Scopus ID)9781509066841 (ISBN)
Conference
44th Annual Conference of the IEEE Industrial Electronics Society, IECON 2018, Washington DC, United States, 20 October 2018 through 23 October 2018
Available from: 2019-03-19 Created: 2019-03-19 Last updated: 2019-03-19Bibliographically approved
Samadaei, E., Iranian, M., Reazanejad, M., Godina, R. & Pouresmaeil, E. (2018). Single-phase active power harmonics filter by Op-Amp circuits and power electronics devices. Sustainability, 10(12), Article ID 4406.
Open this publication in new window or tab >>Single-phase active power harmonics filter by Op-Amp circuits and power electronics devices
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2018 (English)In: Sustainability, ISSN 2071-1050, E-ISSN 2071-1050, Vol. 10, no 12, article id 4406Article in journal (Refereed) Published
Abstract [en]

This paper introduces a new structure for single-phase Active Power Harmonics Filter (APHF) with the simple and low-cost controller to eliminate harmonics and its side effects on low voltage grid. The proposed APHF includes an accurate harmonic detector circuit, amplifier circuit to trap tiny harmonics, switching driver circuit for precise synchronization, and inverter to create injection current waveform, which is extracted from reference signal. The control circuits are based on electrostatic devices consist of Op-Amp circuits. Fast dynamic, simplicity, low cost, and small size are the main features of Op-Amp circuits that are used in the proposed topology. The aim is removing the all grid harmonic orders in which the proposed APF injects an appropriate current into the grid in parallel way. The proposed control system is smart enough to compensate all range of current harmonics. A prototype is implemented in the power electronics laboratory and it is installed as parallel on a distorted grid by the non-linear load (15 APeak-Peak) to verify the compensating of harmonics. The harmonics are compensated from THD% = 24.48 to THD% = 2.86 and the non-sinusoidal waveform is renovated to sinusoidal waveform by the proposed APHF. The experimental results show a good accurate and high-quality performance. 

Keywords
Active power harmonics filter, Electrostatic devices, Hysteresis switching, Op-amp, Power electronics
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-35159 (URN)10.3390/su10124406 (DOI)000455338100072 ()2-s2.0-85057236924 (Scopus ID)
Available from: 2018-12-11 Created: 2018-12-11 Last updated: 2019-03-15Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-8982-5003

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