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Alfredsson, Jon
Publications (10 of 12) Show all publications
Alfredsson, J. (2008). Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies. (Doctoral dissertation). Sundsvall: Mid Sweden University
Open this publication in new window or tab >>Limitations of subthreshold digital floating-gate circuits in present and future nanoscale CMOS technologies
2008 (English)Doctoral thesis, comprehensive summary (Other scientific)
Place, publisher, year, edition, pages
Sundsvall: Mid Sweden University, 2008. p. 129
Series
Mid Sweden University doctoral thesis, ISSN 1652-893X ; 54
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7567 (URN)978-91-85317-97-4 (ISBN)
Public defence
(English)
Supervisors
Available from: 2008-12-10 Created: 2008-12-10 Last updated: 2011-02-06Bibliographically approved
Alfredsson, J. & Aunet, S. (2008). Pseudo floating-gate design limitations in Nano-CMOS with low power supply. In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008.
Open this publication in new window or tab >>Pseudo floating-gate design limitations in Nano-CMOS with low power supply
2008 (English)In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008, 2008Conference paper, Published paper (Refereed)
Abstract [en]

This paper shows simulation results from a recentlyproposed Pseudo Floating-Gate (PFG) technique for use insubthreshold. The design and simulations is performed in a 120nm process CMOS technology and show that there arelimitations that will make subthreshold PFG very difficult tomanufacture with full functionality. The simulations showlimitations in fan-in that will contribute to making it harder tomanufacture structures that have small area or a higharithmetic complexity per active element. It also showbandwidth limitations for the input and output signals.As a complement to the simulations of our PFG design we havealso made a summary of several different kinds of PFGtechniques that are previously developed and some of theirlimitations. The summary also tries to determine where thePFG techniques originates from and present an overview of themost obvious limitations they have.

 

Keywords
low power digital cmos subthreshold floating-gate design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7568 (URN)
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2008-12-10 Last updated: 2010-03-16Bibliographically approved
Alfredsson, J. & Aunet, S. (2008). Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations. In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008.
Open this publication in new window or tab >>Trade-offs for high yield in 90 nm subthreshold floating-gate circuits by Monte Carlo simulations
2008 (English)In: Proceedings of IFIP VLSI-SOC Conference 2008: Rhodes, Greece, October 2008, 2008Conference paper, Published paper (Refereed)
Abstract [en]

The work described in this paper is performed toestimate the influence of statistical process variations andtransistor mismatch that occurs in fabrication and affectfloating-gate digital circuits. These effects will affect and reduce“yield” (percentage of fully functional circuits). Monte Carlosimulations have been performed in a 90 nm to estimate theyield for manufactured floating-gate circuits running withsubthreshold power supply. The power supply, floating-gatecharge voltage (VFGP and VFGN) and transistor sizes have beenvaried during the simulations and the yield has been observed.The simulation results shows that by doubling the minimumsize transistors (length and width) the yield can be much betterthan for minimum size version. A yield of 100% can though notbe expected if the power supply is scaled down below 250 mV.

 

Keywords
low power, digital CMOS, subthreshold, floating-gate design
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-7570 (URN)
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2008-12-10 Last updated: 2010-03-16Bibliographically approved
Alfredsson, J. & Aunet, S. (2007). D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements. In: 2007 NORCHIP: . Paper presented at 25th Norchip Conference, Nov 19-20, 2007, Aalborg, Denmark (pp. 146-149). IEEE conference proceedings
Open this publication in new window or tab >>D-latch for Subthreshold Floating-Gate Circuits Exploiting Threshold Elements
2007 (English)In: 2007 NORCHIP, IEEE conference proceedings, 2007, p. 146-149Conference paper, Published paper (Refereed)
Abstract [en]

When power supply for circuits is reduced the performance will also drop accordingly and to keep up the performance while lowering power supply is an important issue. Floating-gate circuits (FGMOS) have previously been simulated with low power supply and basic digital gates and circuits have already been designed and studied to determine speed and power performance. In this paper we try to expand the circuit library for subthreshold power supply FGMOS circuits by including a floating-gate memory element in terms of a D-latch. Our simulations at 250 mV power supply of a FGMOS D-latch are compared with other D-latches based on static CMOS and mirrored gate elements. The simulations we have performed shows that static CMOS has an advantage in performance of several orders of magnitude in terms of power consumption, while PDP and EDP performance are also better than for FGMOS. When it comes to speed performance, we show that the FGMOS D-latch can be up to 18 times faster than CMOS at the expense of up to three orders of magnitude higher power consumption.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2007
Keywords
Subthreshold, Floating-gate, digital, latch, low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-4451 (URN)000257311000034 ()2-s2.0-50249139531 (Scopus ID)5436 (Local ID)978-1-4244-1516-8 (ISBN)5436 (Archive number)5436 (OAI)
Conference
25th Norchip Conference, Nov 19-20, 2007, Aalborg, Denmark
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2017-10-18Bibliographically approved
Alfredsson, J. & Aunet, S. (2007). Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply. In: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation: . Paper presented at PATMOS - 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep 03-05, 2007, Gothenburg, Sweden (pp. 536-546). Berlin: Springer
Open this publication in new window or tab >>Performance of CMOS and floating-gate full-adders circuits at subthreshold power supply
2007 (English)In: Integrated Circuit and System Design: Power and Timing Modeling, Optimization and Simulation, Berlin: Springer, 2007, p. 536-546Conference paper, Published paper (Refereed)
Abstract [en]

To reduce power consumption in electronic designs, new techniques for circuit design must always be considered. Floating-gate MOS (FGMOS) is one of those techniques and has previously shown potentially better performance than standard static CMOS circuits for ultra-low power designs. One reason for this is because FGMOS only requires a few transistors per gate and still retain a large fan-in. Another reason is that CMOS circuits becomes very slow in subthreshold region and are not suitable in many applications while FGMOS can have a shift in threshold voltage to increase speed performance. This paper investigates how the performance of an FGMOS full-adder circuit will compare with two common CMOS full-adder designs. Simulations in a 120 nm process shows that FGMOS can have up to 9 times better EDP performance at 250 mV. The simulations also show that the FGMOS full-adder is 32 times faster and have two orders of magnitude higher power consumption than that for CMOS.

Place, publisher, year, edition, pages
Berlin: Springer, 2007
Series
Lecture Notes in Computer Science, ISSN 0302-9743 ; 4644/2007
Keywords
low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-5929 (URN)10.1007/978-3-540-74442-9_52 (DOI)000249581300052 ()2-s2.0-37849004999 (Scopus ID)4991 (Local ID)978-3-540-74441-2 (ISBN)4991 (Archive number)4991 (OAI)
Conference
PATMOS - 17th International Workshop on Power and Timing Modeling, Optimization and Simulation, Sep 03-05, 2007, Gothenburg, Sweden
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2016-09-26Bibliographically approved
Alfredsson, J. (2007). Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages. (Licentiate dissertation). Sundsvall: Mittuniversitetet
Open this publication in new window or tab >>Performance of Digital Floating-Gate Circuits Operating at Subthreshold Power Supply Voltages
2007 (English)Licentiate thesis, comprehensive summary (Other academic)
Abstract [en]

All who is involved in electronic design knows that one of the critical issues

in today’s electronic is the power consumption. Designers are always looking for

new approaches in order to reduce currents while still retain performance.

Floating-gate (FGMOS) circuits have previously been shown to be a promising

technique to improve speed and still keep the power consumption low when

power supply is reduced below subthreshold voltage for the transistors.

In this thesis, the goal is to determine how good floating-gate circuits can be

compared to conventional static CMOS when the circuits are working in

subthreshold. The most interesting performance parameters are speed and power

consumption and specifically the Energy-Delay Product (EDP) that is a

combination of those two. To get a view over how the performance varies and how

good the FGMOS circuits are at their best case, the circuits have been designed and

simulated for best case performance.

The investigation also includes trade-offs with speed and power

consumption for better performance, how to select floating-gate capacitances, how

a large circuit fan-in will affect performance and also the influence of different

kinds of refresh circuits.

The first simulations of the FGMOS circuits in a 0.13 μm process have

several interesting results. First of all, in the best case it is shown that FGMOS has

potential to achieve up to 260 times in better EDP-performance compared to CMOS

at 150 mV power supply. Continuing with simulations of FGMOS capacitances

shows that minimum floating-gate capacitance can be as small as 400 fF and more

realistic performance shows that EDP is 37 times better for FGMOS (with parasitic

capacitances included). Other aspects of FGMOS design have been to look at how

refresh circuits will affect performance (semi-floating-gate circuits) and how a

larger fan-in will change noise margin and EDP. It turns out that refresh circuits

with the same transistor size does not give a noticeable change in performance

while an increase of 8 times in size will give between 5 and 10 times wors EDP.

When it comes to fan-in the simulations shows that a maximum fan-in of 5 is

possible at 250 mV supply and it decrease to 3 when supply voltage is reduced to

150 mV.

Finally, it should be kept in mind that tuning the performance of FGMOS

circuits with trade-offs and by changing the floating-gate voltages to achieve

results like the ones stated above will also always affect the noise margins, NM, of

the circuits. As a consequence of this, the NM will sometimes be so close to 1 that a

fabricated circuit with that NM may not be as functional as simulations suggests.

The probability to design functional FGMOS circuits in subthreshold does not

seem to be a problem though.

Place, publisher, year, edition, pages
Sundsvall: Mittuniversitetet, 2007. p. 44
Series
Mid Sweden University licentiate thesis, ISSN 1652-8948 ; 18
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-9333 (URN)91-85317-35-7 (ISBN)
Presentation
(English)
Opponent
Supervisors
Available from: 2009-07-10 Created: 2009-07-10 Last updated: 2011-02-06Bibliographically approved
Alfredsson, J., Aunet, S. & Oelmann, B. (2007). Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure. In: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA: . Paper presented at 20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems, jan 06-10, 2007, Bangalore, india (pp. 314-317). IEEE conference proceedings
Open this publication in new window or tab >>Small Fan-in Floating-gate Circuits with Application to an Improved Adder Structure
2007 (English)In: 20TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS - TECHNOLOGY CHALLENGES IN THE NANOELECTRONICS ERA, IEEE conference proceedings, 2007, p. 314-317Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. One reason for this is because FGMOS only requires a few transistors per gate while it still can have a large fan-in. When power supply is reduced to subthreshold region it will influence the maximum fan-in that is possible to use in designs. In this paper we have investigated how the performance of FGMOS circuits will change in subthreshold region. Simulation in a 120 nm process technology shows that FGMOS will not be working for circuits that have a large fan-in and might not be useable for many designs. At 250 mV power supply it can have a maximum fan-in of 5 and for 150 mV the maximum is 3. FGMOS simulations of an improved full-adder structure with fan-in of 3 is also proposed and compared to a conventional structure with fan-in of 5. It is shown that the improved full-adder with fan-in 3 will have more than 36 times better energy-delay product (EDP)

Place, publisher, year, edition, pages
IEEE conference proceedings, 2007
Series
International Conference on VLSI Design, Proceedings, ISSN 1063-9667
Keywords
Low power, Digital CMOS, Floating-gate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3900 (URN)10.1109/VLSID.2007.143 (DOI)000245425300045 ()2-s2.0-48349148523 (Scopus ID)4258 (Local ID)978-0-7695-2762-8 (ISBN)4258 (Archive number)4258 (OAI)
Conference
20th International Conference on VLSI Design held jointly with the 6th International Conference on Embedded Systems, jan 06-10, 2007, Bangalore, india
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2017-10-20Bibliographically approved
Alfredsson, J. & Oelmann, B. (2006). Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold. In: Proceedings - IEEE International Symposium on Circuits and Systems: . Paper presented at ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems; Kos; Greece; 21 May 2006 through 24 May 2006 (pp. 4341-4344). IEEE conference proceedings, Article ID 1693590.
Open this publication in new window or tab >>Capacitance Selection for Digital Floating Gate Circuits Operating in Subthreshold
2006 (English)In: Proceedings - IEEE International Symposium on Circuits and Systems, IEEE conference proceedings, 2006, p. 4341-4344, article id 1693590Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper we have investigated how the floating-gate capacitances can be selected to achieve the best performance in floating-gate circuits operating at subthreshold power supply. Based on circuit simulations in a 120nm process technology, it is shown that the EDP offers a reduction of more than one order of magnitude for FGMOS with capacitance selection in comparison to static CMOS circuits. This paper also deals with the possibilities available for trade-offs between lower power consumption and higher speed to achieve a better performance for FGMOS than for static CMOS. The main cost involved in achieving these performance improvements is reduced noise margins

Place, publisher, year, edition, pages
IEEE conference proceedings, 2006
Series
IEEE INTERNATIONAL SYMP ON CIRCUITS AND SYSTEMS, ISSN 0277-674X
Keywords
low power
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3743 (URN)10.1109/ISCAS.2006.1693590 (DOI)000245413504168 ()2-s2.0-34547241637 (Scopus ID)4017 (Local ID)978-0-7803-9389-9 (ISBN)4017 (Archive number)4017 (OAI)
Conference
ISCAS 2006: 2006 IEEE International Symposium on Circuits and Systems; Kos; Greece; 21 May 2006 through 24 May 2006
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2016-10-05Bibliographically approved
Alfredsson, J. & Oelmann, B. (2006). Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs. In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3. Paper presented at 13th IEEE International Conference on Electronics, Circuits and Systems, Dec 10-13, 2006, Nice, France (pp. 1296-1299).
Open this publication in new window or tab >>Influence of Refresh Circuits Connected to Low Power Digital Quasi-Floating gate Designs
2006 (English)In: 2006 13TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS 1-3, 2006, p. 1296-1299Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption, floating-gate circuits (FGMOS) have been considered to be a potentially better technique than standard static CMOS circuits. For each new generation of process technology the thickness of the transistor gate-oxide will be reduced. This will increase charge leakage in FGMOS circuits and it is therefore necessary to introduce techniques to keep the charge in the node. In this paper we investigate how the most commonly used refresh circuits (quasi-and pseudo-floating gate) affect the performance when they are connected to an FGMOS circuit working with subthreshold power supply. The simulations show that refresh circuits equal in size compared to FGMOS will not have much influence on performance while it is reduced up to an order in magnitude when the size increase 8 times. This strong impact from the refresh circuitry also indicates that it might not be an option for future technologies.

Keywords
Low Power, Digital CMOS, Floating-gate
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-3899 (URN)10.1109/ICECS.2006.379719 (DOI)000252489600324 ()4257 (Local ID)978-1-4244-0394-3 (ISBN)4257 (Archive number)4257 (OAI)
Conference
13th IEEE International Conference on Electronics, Circuits and Systems, Dec 10-13, 2006, Nice, France
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2011-02-06Bibliographically approved
Alfredsson, J., Aunet, S. & Oelmann, B. (2005). Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold. In: Proceedings of IFIP VLSI-SOC 2005: International Conference on Very Large Scale Integration. Paper presented at IFIP International Conference on Very Large Scale Interaction (pp. 229-232). Edith Cowan Univ
Open this publication in new window or tab >>Basic Speed and Power Properties of Digital Floating-gate Circuits Operating in Subthreshold
2005 (English)In: Proceedings of IFIP VLSI-SOC 2005: International Conference on Very Large Scale Integration, Edith Cowan Univ , 2005, p. 229-232Conference paper, Published paper (Refereed)
Abstract [en]

For digital circuits with ultra-low power consumption,floating-gate circuits have been considered to be a techniquepotentially better than standard static CMOS circuits.By having a DC offset on the floating gates, theeffective threshold voltage of the floating-gate transistoris adjusted and the speed and power performance can bealtered. In this paper the basic performance related propertiessuch as power, delay, power-delay product (PDP),and energy-delay product (EDP) for floating-gate circuitsoperating in subthreshold are investigated. Based on circuitsimulations in a 120nm process technology, it isshown that for the best case, the power can be reducedapproximately by one order of magnitude at the expenseof increased delay, while the PDP is more or less constantin comparison to static CMOS. The EDP can be reducedby two orders of magnitude at the expense of reducednoise margins.

Place, publisher, year, edition, pages
Edith Cowan Univ, 2005
Keywords
low power electronics subthreshold floating-gate
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8006 (URN)
Conference
IFIP International Conference on Very Large Scale Interaction
Projects
STC - Sensible Things that Communicate
Available from: 2009-01-07 Created: 2009-01-07 Last updated: 2012-02-16Bibliographically approved
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