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Hesselbom, Hjalmar
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Publications (10 of 11) Show all publications
Mbairi, F. D. & Hesselbom, H. (2009). Microwave bandstop filters using novel artificial periodic substrate electromagnetic band gap structures. IEEE transactions on components and packaging technologies (Print), 32(2), 273-282
Open this publication in new window or tab >>Microwave bandstop filters using novel artificial periodic substrate electromagnetic band gap structures
2009 (English)In: IEEE transactions on components and packaging technologies (Print), ISSN 1521-3331, E-ISSN 1557-9972, Vol. 32, no 2, p. 273-282Article in journal (Refereed) Published
Abstract [en]

Novel microwave and millimeterwave (mm-wave) bandstop filters using artificial periodic substrate electromagnetic bandgap (EBG) are investigated in this paper. Three types of microstrip structures using periodically modified trace width, patterned dielectric substrate, and periodically modified ground plane are treated, respectively. By periodically modifying either the width of the conductor trace, the substrate height, or the dielectric constant of a standard microstrip transmission line, it has been possible to design microwave bandstop filter functions with wide stopband characteristics and reduced size, compared to conventional microwave/RF filter structures. Commercial electronic design automation (EDA) and computational electromagnetic tools such as Agilent's advanced design system (ADS) and CST Microwave Studio are used in the design and simulations of these filter structures. The effects of the physical parameters of the structures on the filter characteristic are studied. The design procedure and simulation results are described and possible applications of these filter structures are discussed in this paper. A particularly wide stopband is achieved by the circuits presented in this paper, which use only a few cell elements. A significant performance improvement of microstrip patch antenna has been observed by implementing one of the presented EBG periodic substrate structures.

National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-9600 (URN)10.1109/TCAPT.2009.2018833 (DOI)000268282800007 ()2-s2.0-68349154344 (Scopus ID)
Available from: 2009-09-01 Created: 2009-09-01 Last updated: 2017-12-13Bibliographically approved
Mbairi, F., Siebert, W. P. & Hesselborn, H. (2008). High-frequency transmission lines crosstalk reduction using spacing rules. IEEE transactions on components and packaging technologies (Print), 31(3), 601-610
Open this publication in new window or tab >>High-frequency transmission lines crosstalk reduction using spacing rules
2008 (English)In: IEEE transactions on components and packaging technologies (Print), ISSN 1521-3331, E-ISSN 1557-9972, Vol. 31, no 3, p. 601-610Article in journal (Refereed) Published
Abstract [en]

High-frequency transmission lines crosstalk reduction using spacing rules is treated in this paper. Two of the most popular planar transmission line configurations, namely microstrip and stripline, commonly used in printed circuit boards and radio frequency/microwave integrated circuits, are considered in this work. The trace separation between two adjacent transmission lines of each type is stepwise increased as function of the trace width. The single-ended transmission line structures are numerically investigated by a frequency-based 3-D full-wave electromagnetic analysis tool. A particular case using coated microstrip transmission lines has been fabricated, along with some calibration structures, to allow direct measurement and experimental analysis of crosstalk between the single-ended transmission lines. The test structures are characterized at high-frequency (up to 20 GHz) with scattering parameters using a vector network analyzer. The experimental results are compared with the simulation data, and some conclusions and suggestions on the impact and use of spacing rules for high-frequency crosstalk reduction between single-ended transmission lines are presented. These investigations emphasize the necessity of reevaluating classical design rules for their suitability in high-frequency applications.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2008
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8346 (URN)10.1109/TCAPT.2008.2001163 (DOI)000259573600010 ()2-s2.0-54849376700 (Scopus ID)
Note

VR-Materials Science

Available from: 2009-01-19 Created: 2009-01-19 Last updated: 2017-12-14Bibliographically approved
Mbairi, F. D., Siebert, W. P. & Hesselbom, H. (2007). On the problem of using guard traces for high frequency differential lines crosstalk reduction. IEEE transactions on components and packaging technologies (Print), 30(1), 67-74
Open this publication in new window or tab >>On the problem of using guard traces for high frequency differential lines crosstalk reduction
2007 (English)In: IEEE transactions on components and packaging technologies (Print), ISSN 1521-3331, E-ISSN 1557-9972, Vol. 30, no 1, p. 67-74Article in journal (Refereed) Published
Abstract [en]

In this paper, the problem of using guard traces for reducing crosstalk between differential transmission line pairs is investigated, both experimentally and by full-wave electromagnetic (EM) simulations. Different cases of differential lines crosstalk are treated with and without guard trace separation between the differential line pairs. Coated microstrip printed circuit board test structures including thru-reflect-line calibration standards are designed and fabricated on a high frequency laminate material, allowing direct measurement of crosstalk between adjacent differential line pairs in the absence and in the presence of guard traces stitched with vias of regular spacing. The test structures are characterized with mixed-mode scattering parameters using a physical layer test system. Different configurations (of differential line pairs) without guard trace, with floating guard traces (which are terminated and nonterminated) and with a solid guard trace separation are investigated using a High Frequency Structure Simulator (a commercial full-wave 3-D EM simulation tool). The experimental data are compared with the simulation results, and some conclusions and guidelines on the effect of guard traces for alleviating crosstalk between differential transmission lines are presented.

Keywords
Coated microstrip differential transmission lines, Coupling, Guard trace, High frequency crosstalk, S-parameters measurement, Signal integrity, Thru-reflect-line (TRL) calibration
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-8469 (URN)10.1109/TCAPT.2007.892072 (DOI)000245418400009 ()2-s2.0-34147122524 (Scopus ID)
Note

VR-Materials Science

Available from: 2009-01-26 Created: 2009-01-26 Last updated: 2017-12-14Bibliographically approved
Norberg, G., Dejanovic, S. & Hesselbom, H. (2006). Contact Resistance of Thin Metal Film Contacts. IEEE transactions on components and packaging technologies (Print), 29(2), 371-378
Open this publication in new window or tab >>Contact Resistance of Thin Metal Film Contacts
2006 (English)In: IEEE transactions on components and packaging technologies (Print), ISSN 1521-3331, E-ISSN 1557-9972, Vol. 29, no 2, p. 371-378Article in journal (Refereed) Published
Abstract [en]

To be able to reduce the size of products having electronic devices, it becomes more and more important to miniaturize the electro-mechanical parts of the system. The use of micro mechanical connectors and contact structures implies the need of methods for estimating the properties of such devices. This work will, by use of finite element modeling, treat the influence of a thin film constituting at least one of the contacting members of an electrical contact. The error introduced by using the traditional Maxwell/Holm contact constriction resistance theory will be investigated. Numerical methods are used to present a way to approximate the total resistance for the thin metal film contact.

Keywords
Contact Resistance, Constriction Resistance
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2954 (URN)10.1109/TCAPT.2006.875891 (DOI)000237982600020 ()2-s2.0-33744831222 (Scopus ID)2683 (Local ID)2683 (Archive number)2683 (OAI)
Note

VR-Materials Science

Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
Norberg, G., Dejanovic, S. & Hesselblom, H. (2006). Very High Density Interconnect Elastomer Chip. IEEE Transactions on Advanced Packaging, 29(2), 202-210
Open this publication in new window or tab >>Very High Density Interconnect Elastomer Chip
2006 (English)In: IEEE Transactions on Advanced Packaging, ISSN 1521-3323, E-ISSN 1557-9980, Vol. 29, no 2, p. 202-210Article in journal (Refereed) Published
Abstract [en]

The integration of more and more functionality into smaller and smaller form factor electronic products, drives the need for denser chip to substrate interconnect systems. As the number of I/O pins increases the use of area array chips or packages becomes inevitable. Metal patterned elastomer chip sockets have now been improved to work with contact densities as high as 80 000 contacts/cm2 corresponding to a pitch of 36 µm. Sockets with 10 000 contacts and a 72 µm pitch have survived more than 400 cycles in air to air thermal cycling chambers as well as freezing shocks caused by dipping into liquid nitrogen. Although the daisy chain test circuits breaks for temperatures lower than -50 C and higher than 90 C, they always return to the initial resistance values when entering the normal temperature range. The combination of a gold to gold contact interface and the elastic features of the contact bumps, makes this socket an ideal compliance layer between bare chips and different types of carrier substrates, reducing the problems caused by thermomechanical mismatch between the substrate and the chip. Bad dies can easily be replaced, since the chip is not soldered or glued to the socket. The size and the possibility to control the geometry of the contacts, provides means to maintain a good high frequency characteristic impedance matching all the way to the chip pad.

Keywords
Chip socket, Chip-first, Flip-chip, High-density interconnect, Multichip modules, Packaging, Silicone elastomer, Thermal fatigue, Thermal stress
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2952 (URN)10.1109/TADVP.2006.871178 (DOI)000237429900001 ()2-s2.0-33646534157 (Scopus ID)2681 (Local ID)2681 (Archive number)2681 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2017-12-12Bibliographically approved
Mbairi, F. D. & Hesselbom, H. (2005). High frequency design and characterization of SU-8 based conductor backed coplanar waveguide transmission lines. In: Proceedings of the International Symposium and Exhibition on Advanced Packaging Materials Processes, Properties and Interfaces: . Paper presented at 2005 10th International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces; Irvine, CA; United States; 16 March 2005 through 18 March 2005 (pp. 243-248). IEEE conference proceedings, Article ID 1432083.
Open this publication in new window or tab >>High frequency design and characterization of SU-8 based conductor backed coplanar waveguide transmission lines
2005 (English)In: Proceedings of the International Symposium and Exhibition on Advanced Packaging Materials Processes, Properties and Interfaces, IEEE conference proceedings, 2005, p. 243-248, article id 1432083Conference paper, Published paper (Refereed)
Abstract [en]

The epoxy-based negative photoresist SU8 is widely used within the MEMS (Micro-Electro-Mechanical Systems) community, and is well known for its ability to form thick layers with high aspect ratios and for its chemical resistance. However, only a few papers have investigated the electrical properties of this material and mostly within the MEMS area or at lower frequency ranges.

This paper presents the design and characterization of conductor-backed coplanar waveguide (CBCPW) transmission lines using SU-8 dielectric material. The coplanar transmission lines are carefully designed using EDA tools, and fabricated on a metallized glass substrate coated with SU-8 material. S-parameter measurements are performed from 45 MHz to 50 GHz using a vector network analyzer and a probe station. From these measurements, transmission line parameters such as characteristic impedance, attenuation constant, effective dielectric constant, loss tangent, etc, are determined. The design procedure, fabrication process and measurement results are described in this paper.

To our knowledge, this is the first time the SU-8 material is characterized in Microelectronics using CBCPW transmission lines.

Place, publisher, year, edition, pages
IEEE conference proceedings, 2005
Keywords
microwave measurements; conductor-backed coplanar waveguides (CBCPW) transmission lines; coplanar waveguides (CPW); dielectric measurement; high frequency electrical characterization
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-11863 (URN)10.1109/ISAPM.2005.1432083 (DOI)000230430400050 ()2-s2.0-33746556795 (Scopus ID)0-7803-9085-7 (ISBN)
Conference
2005 10th International Symposium on Advanced Packaging Materials: Processes, Properties and Interfaces; Irvine, CA; United States; 16 March 2005 through 18 March 2005
Available from: 2010-07-15 Created: 2010-07-15 Last updated: 2016-09-29Bibliographically approved
Hesselbom, H., Norberg, G., Dejanovic, S. & Haglund, D. (2004). Solder and adhesive free chip assembly using elastic chip sockets: Concept, Manufacture and Preliminary Investigations. In: Proceedings of 2004 International IEEE Conference on the Asian Green Electronics (AGEC) (pp. 12-17). Piscataway, NJ, USA: IEEE
Open this publication in new window or tab >>Solder and adhesive free chip assembly using elastic chip sockets: Concept, Manufacture and Preliminary Investigations
2004 (English)In: Proceedings of 2004 International IEEE Conference on the Asian Green Electronics (AGEC), Piscataway, NJ, USA: IEEE , 2004, p. 12-17Conference paper, Published paper (Other academic)
Abstract [en]

Flip Chip connections enormously reduces the amount of solder as compared to mounting packaged devices, apart from also offering superior high frequency properties and placement density. However, when assembling chips to substrates having different thermal expansion coefficient, the solder balls are exposed to strain, the more so the denser the connections (and consequently smaller balls), and the higher the power densities, resulting in wider temperature cycles. This will usually result in loss of contact reliability. Using other materials than solder or using underfills may partially improve the situation, but causes other problems. In order to test another concept maintaining or exceeding the excellent HF and density properties of conventional Flip Chip, while practically eliminating the thermal mismatch problems and providing effortless chip replacement, the Elastic Chip Socket was developed. Silicone elastomer was molded in a precision mold made using anisotropic etching of Si. These structures were subsequently metallized and the metal patterned using electro plated resist. So far functional chip sockets with pin densities of 45 000 pins per cm2 (22 500 simultaneously functional connections to a 7 x 7 mm die) and more have been achieved which endure multiple repeated matings and quick temperature cycling between -40 °C and +90 °C. The following is a summary of the group's achievement this far, Oct. 2003

Place, publisher, year, edition, pages
Piscataway, NJ, USA: IEEE, 2004
Keywords
Chip Assembly
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-928 (URN)10.1109/AGEC.2004.1290858 (DOI)2792 (Local ID)0-7803-8203-X (ISBN)2792 (Archive number)2792 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2011-04-08Bibliographically approved
Norberg, G., Dejanovic, S. & Hesselbom, H. (2003). Elastomer Chip Sockets for Reduced Thermal Mismatch Problems and Effortless Chip Replacement, Preliminary Investigations. IEEE Transactions on Advanced Packaging, 26(1), 33-40
Open this publication in new window or tab >>Elastomer Chip Sockets for Reduced Thermal Mismatch Problems and Effortless Chip Replacement, Preliminary Investigations
2003 (English)In: IEEE Transactions on Advanced Packaging, ISSN 1521-3323, Vol. 26, no 1, p. 33-40Article in journal (Refereed) Published
Abstract [en]

To avoid the problem with thermo-mechanical stress induced fatigue using conventional flip-chip mounting of bare chips, an elastic chip socket has been developed. The socket is made by casting silicone elastomer into micro structured silicon molds to form micro bump arrays. After the elastomer is cured and released from the mold, a metal layer is deposited and patterned. A chip is placed in the socket utilizing guiding structures for chip self alignment. The chip is then held in place by a spring loaded back-plate which can also serve as a heat sink for highly effective chip cooling. Since no adhesives, underfills or solders are used, the rework process becomes very simple and it can also be repeated many times for the same socket. Initial contact resistance and thermo-mechanical robustness measurements indicates that this type of sockets could work as a superior replacement for conventional flip-chip technologies in many applications. The particular design of the contact bumps results in metal structures that resemble (although up side down) and are scalable as those in the Chip-First technology. Preliminary thermal shock experiments from room temperature to liquid nitrogen and back show good survival. Thus, this new chip interconnect method indicates the possibility of getting the advantages of the Chip-First technology while eliminating the demand of placing the chip first. The concept will work for chips with rim positioned pads as well as for high density area arrays.

Keywords
Chip-first, chip socket, flip chip, multi-chip modules, packaging, silicone elastomer, thermal fatigue, thermal stress
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-2964 (URN)10.1109/TADVP.2003.811362 (DOI)000182870300005 ()2-s2.0-0037604515 (Scopus ID)1569 (Local ID)1569 (Archive number)1569 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2016-10-24Bibliographically approved
Koptioug, A. & Hesselbom, H. (2003). Some Aspects of Modelling of Dense High Speed TL Interconnects for Printed Circuit Boards. In: GigaHertz 2003: Proceedings from the Seventh Symposium, November 4–5, 2003, Linköping, Sweden. Linköping
Open this publication in new window or tab >>Some Aspects of Modelling of Dense High Speed TL Interconnects for Printed Circuit Boards
2003 (English)In: GigaHertz 2003: Proceedings from the Seventh Symposium, November 4–5, 2003, Linköping, Sweden, Linköping, 2003Conference paper, Published paper (Other academic)
Abstract [en]

In this paper we present some results of the ongoing research aimed at studying the limitations attached to the increase in transmission line (TL) density for the high speed interconnects at the board, multi-chip module and on-chip integration levels. For any interconnect solution the important quality in the frequency band of interest is the signal to noise ratio obtainable, where noise could be due to additional amplification required, TL itself and any cross talk signal picked up by the line. First part of the paper deals with modeling the coupling between two TL sections in the attempt to formulate simple guidelines on how to chose the TL dimensions and adjacent trace separation to maintain reasonably low trace coupling. Second part of the paper deals with the influence of TL cross- sectional parameter upon the high frequency losses. Area efficiency parameter is introduced to allow the measure of the tradeoff between obtaining smaller loss (with wider central strips) and smaller cross talk in order to obtain the best possible throughput per board cross section at any bit error rate.

Place, publisher, year, edition, pages
Linköping: , 2003
Series
Linköping Electronic Conference Proceedings, ISSN 1650-3740 ; 8
Keywords
Transmission Lines, High Frequency
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-5621 (URN)2814 (Local ID)2814 (Archive number)2814 (OAI)
Available from: 2008-09-30 Created: 2008-09-30 Last updated: 2011-04-06Bibliographically approved
Dejanovic, S., Hesselbom, H. & Norberg, G. Manufacturing of Via Holes in Silicone Elastomer.
Open this publication in new window or tab >>Manufacturing of Via Holes in Silicone Elastomer
(English)Manuscript (Other (popular science, discussion, etc.))
Abstract [en]

In this work a possibility of making via holes in silicone elastomer was investigated. The methods that were taken into consideration were punching, mechanical drilling, laser drilling and RIE. Laser drilling and RIE were found to be viable and both were tried. Laser drilling of silicone elastomer has shown a big problem with burnt residues and has to be investigated much further to be usable. RIE of silicone elastomer is reported in this work. Several phenomena were observed. The etch-residues can be removed by washing them away in an ultra sonic water bath and subsequently totally removed by using a lift-off process based on wet Cu etch. A good anisotropy was achieved by applying CF4 plasma. Gradually broadening of the openings in the etch mask has contributed to a favorable etch profile and thus easier metallization of side-walls of via holes.

Keywords
silicone elastomer, dry etch, RIE, via hole
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:miun:diva-6246 (URN)2685 (Local ID)2685 (Archive number)2685 (OAI)
Note
Submitted to IEEE Transaction on Components and Packaging Technologies, Feb 2004Available from: 2009-02-18 Created: 2009-02-18 Last updated: 2011-04-08Bibliographically approved
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